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The engineer will be responsible for DFT insertion, scan chain implementation, and developing ATPG patterns to meet design test coverage goals. They will also perform failure analysis, debug testbenches, and collaborate with cross-functional teams to ensure high-quality silicon designs.
Candidates must have 10-20 years of professional experience in SoC/ASIC digital design with a strong focus on DFT. Proficiency in scan technologies, MBIST, ATPG, and Verilog testbench debugging is required, along with the ability to work independently in a fast-paced environment.
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
Requirements;
US citizenship preferred.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US
