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Full-time
postgraduate degree
Posted 1d ago
~40 hrs/week
Responsibilities
The Principal Product Engineer will serve as the primary technical interface for strategic customer engagements, facilitating the deployment of DDR PHY IP solutions. Responsibilities include debugging customer silicon issues, performing onsite support, and utilizing AI-powered tools to enhance productivity and technical deliverables.
Requirements
Candidates must hold an M.S. or PhD in Electrical/Computer Engineering with at least 5 to 10 years of relevant experience in memory PHY and DRAM. Strong expertise in post-silicon bringup, lab equipment, and signal/power integrity analysis is required.
Full job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Product Engineer - DDR IP
Location: Shanghai, China
About Us
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the world’s most innovative companies, delivering extraordinary electronic products—from chips to boards to systems—for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success.
Position Overview
This is an exceptional opportunity to become part of the dynamic and expanding Product Engineering team within the DDR IP division at Cadence Design Systems. We are seeking a highly skilled Principal Product Engineer to serve as the primary technical interface for strategic customer engagements, facilitating the deployment of our cutting-edge DDR PHY IP solutions. This role is hands-on and pivotal, operating in a post-silicon environment and demanding a comprehensive understanding across multiple technical domains. Joining our team means contributing to innovative projects that drive the future of electronic design, while collaborating with industry-leading experts in a culture focused on excellence and customer success.
Key Responsibilities
Protocol & Physical Layer: Demonstrate a strong understanding of DDR, LPDDR and GDDR implementations.
Primary Technical Liaison: Act as the main technical contact for debugging customer silicon issues, both for systems and ATE
Lab Equipment Proficiency: Demonstrate hands-on experience with oscilloscopes, BERTs, protocol exercisers, and analyzers.
Signal Integrity (SI) and Power Integrity (PI): Understand SI and PI requirements for the IP and assist in diagnosing related hardware issues.
Onsite Support: Travel to customer sites (about 10% of the time) for bringup and debug of silicon issues.
Technical Issue Management: Own support cases filed by the customer on SFDC.Use tools such as Sherlock and JIRA to document and coordinate issue debugging.
AI Incorporation: Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables. Apply AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets.
Required Skills & Qualifications
M.S. Electrical/Computer Engineering (or similar degree) and 10 + years of experience or PhD and 5+ Years of relevant experience
Experience working with Memory PHY, Memory Controller and DRAM
Experience using advanced mixed signal verification, and system simulation tools.
Strong debug and problem-solving skills.
Strong background in supporting Post Silicon bringup and debug.
Familiarity with advanced technology nodes (7nm and below) is a plus.
Strong presentation and communication skills required.
Experience with lab equipment to reproduce customer failures in the lab.
Familiarity with SI/PI analysis concepts and able to diagnose hardware issues
We’re doing work that matters. Help us solve what others can’t.
Related keywords
DDR IPPHY IPPost-siliconSignal IntegrityPower IntegrityMixed Signal VerificationSystem SimulationOscilloscopesBERTsProtocol ExercisersMemory ControllerDRAM7nmAI-powered developmentIntelligent System DesignCustomer Support
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US