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Product Engineer II (EMIR / PDN Analysis & Power Integrity)
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Product Engineer II (EMIR / PDN Analysis & Power Integrity)
Austin, Texas, United States · On-site
$102k–$189k/yr
Mid level
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities • Be part of the product engineering team working on Power Noise Reliability analysis pla…
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Skills: Formal Verification, Verilog, System Verilog Assertions, Python, TCL
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Full-time
Posted 15d ago
~40 hrs/week
Responsibilities
The engineer will be responsible for DFT insertion, scan chain implementation, and developing ATPG patterns to meet design test coverage goals. They will also perform failure analysis, debug testbenches, and collaborate with cross-functional teams to ensure high-quality silicon designs.
Requirements
Candidates must have 10-20 years of professional experience in SoC/ASIC digital design with a strong focus on DFT. Proficiency in scan technologies, MBIST, ATPG, and Verilog testbench debugging is required, along with the ability to work independently in a fast-paced environment.
Full job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
Requirements;
US citizenship preferred.
Prior 10-20 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
Should possess intimate knowledge of DFT insertion flows
Basic scan chain insertion using synthesis or other software tools
Experience in compression scan insertion, LBIST and other scan technologies
Intimate knowledge of memory build-in self-test (MBIST)
Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
Debug and Analysis of failures to improve fault coverage
Verification of ATPG testbenches and debugging root cause of simulation mis-compares
Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
Knowledge of timing analysis and equivalency checks would be added bonus
Ability to work in collaborative team environment
Prior experience with Cadence tools and flows is highly desirable
Should be able to finish DFT tasks independently
Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
Self-driven and committed individual who can work in a fast-paced project environment
We’re doing work that matters. Help us solve what others can’t.
Related keywords
SoCASICDFTDesign for TestScan chainMBISTATPGVerilogSynthesisVerificationJTAGIEEE1500IEEE1687Timing analysisEquivalency checksCadence
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US