At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our North America Palladium and Protium HW Development team and help shape the future of system-level chi…
Skills: Digital design, Computer architecture, System-level verification, Emulation, FPGA prototyping
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Product Engineer II (EMIR / PDN Analysis & Power Integrity)
Austin, Texas, United States · On-site
$102k–$189k/yr
Mid level
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Product Engineer II (EMIR / PDN Analysis & Power Integrity)
Austin, Texas, United States · On-site
$102k–$189k/yr
Mid level
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities • Be part of the product engineering team working on Power Noise Reliability analysis pla…
Skills: Power Integrity, 3DIC Analysis, IR Drop Analysis, VLSI, Digital Logic Design
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software e…
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software e…
Skills: Formal Verification, Verilog, System Verilog Assertions, Python, TCL
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$154k–$286k/yr
Full-time
bachelor degree, postgraduate degree
Paid vacation, Paid holidays, 401(k) plan with employer match, Employee stock purchase plan, Medical insurance, Dental insurance
Posted 15d ago
Apply by Dec 31
~40 hrs/week
Responsibilities
You will collaborate with customers and engineering teams to deploy and optimize advanced protocol solutions on Palladium and Protium platforms. Additionally, you will lead technical evaluations, perform root-cause debugging, and develop innovative verification methodologies for complex chip designs.
Requirements
Candidates must have a BS with at least 10 years of experience or an MS with at least 7 years of experience in digital design and system-level verification. Strong proficiency in hardware description languages, C/C++, and deep technical knowledge of emulation and FPGA prototyping are required.
Full job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Join our North America Palladium and Protium HW Development team and help shape the future of system-level chip design verification. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence’s market-leading hardware emulation and FPGA prototyping platforms. You will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D — develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers’ most complex architectural and high-Speed Protocol challenges.
Key Responsibilities
Customer Enablement & Solutions: Collaborate with frontline engineering teams and customers to develop, deploy, productize, and optimize advanced protocol solutions on Palladium and Protium platforms.
Requirements & Feature Development: Define and develop customer-specific emulation and prototyping requirements, focusing heavily on leading edge high-speed interfaces and memory protocols (e.g., PCIe, CXL).
Advanced Solutions Engineering: Drive the development of advanced acceleration FW + FPGA system solutions, establish robust verification methodologies, and support the operation and maintenance of Cadence emulation tools.
Root-Cause Debugging: Triage and resolve complex, systemic issues across the hardware/software boundary, optimizing driver behavior, protocol compliance, and overall system stability.
Evaluations & Benchmarking: Lead technical evaluations and develop high-performance benchmarks to demonstrate the competitive advantages of Cadence hardware platforms.
Technical Presentation: Create and deliver impactful technical presentations, white papers, and product demonstrations for existing and prospective customers.
What You’ll Need
BS with a minimum of 10 years of experience or MS with a minimum of 7 years of experience
Strong fundamentals in digital design, computer architecture, and system‑level verification
Have deep technical knowledge in a few of; Simulation (Advanced Testbench), Emulation (TBA & ICE) & FPGA Prototyping
Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++
Understanding of standard interconnect or IO protocols used in modern chip designs
Good debugging skills using waveforms, logs, and protocol analyzers
Ability to work across hardware and software boundaries.
Excellent communication, and interpersonal skills, ability to work in an international environment
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US