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Full-time
bachelor degree, postgraduate degree
Posted 19d ago
~40 hrs/week
Responsibilities
Lead and mentor a team of RTL design engineers to develop microarchitectural features for IPs and subsystems. Oversee the full design cycle from RTL development and optimization to pre-silicon verification and signoff.
Requirements
Requires over 10 years of experience in front-end design or verification with a degree in Engineering or Computer Science. Candidates must have a proven track record in IP/SoC integration and expertise in RTL design and synthesis tools.
Full job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.
This is a leadership role where you will be responsible for:
Technical Leadership:
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
Design & Microarchitecture:
Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
RTL Development:
Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
Verification & Signoff:
Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
Collaboration:
Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.
Qualifications:
10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
Proven experience in leading and managing complex engineering projects
Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
Expert in RTL design (Verilog), simulators debuggers
Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
Experience in driving results in multi-disciplinary organization
Desirable:
A Self-motivated person with good communication and design management skills
Experience with Cadence front end toolset
We’re doing work that matters. Help us solve what others can’t.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US