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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description The candidate will be responsible for driving customer engagement on parasitic extraction solu…
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Boston, Massachusetts, United States · On-site
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Drive customer engagement for parasitic extraction solutions and resolve complex technical issues to ensure successful tape-outs. Act as the primary technical interface between customers, application engineering teams, and R&D for tool improvements and methodology deployment.
Requires a B.S. or M.S. in Microelectronics, Electrical, or a similar engineering field with over 3 years of industry experience. Candidates must have a strong understanding of ASIC design flows and proficiency with EDA tools like Quantus, Virtuoso, or Innovus.
Job Description
The candidate will be responsible for driving customer engagement on parasitic extraction solutions, including transistor-level and cell-level extraction, RC/RLC analysis, and signoff validation using Quantus.
The candidate will work closely with customers to analyze and resolve complex technical issues, ensuring high-quality extraction results and successful tape-outs.
The candidate will serve as a key interface between customers, AE teams, and R&D, facilitating efficient communication, feedback loop, and issue resolution.
The candidate will support methodology setup and deployment, including flow enablement, best practices, and usage guidance for parasitic extraction and related design flows.
The candidate will participate in customer training, technical reviews, and solution delivery, ensuring effective adoption of Quantus solutions.
The candidate will have the opportunity to work on advanced-node designs, large-scale parasitic networks, and next-generation EDA technologies.
Primary Responsibilities:
o Provide technical support and engagement for parasitic extraction flows, including flow enablement and methodology deployment
o Work with customers to analyze design challenges and provide professional guidance and solutions
o Act as the primary interface between customers, AE teams, and R&D to drive issue resolution and feature improvements
o Support customer training activities and provide best practices for tool usage and design flows
o Assist in debugging complex design or flow issues and ensure timely resolution
o Participate in technical reviews and support customer tape-out readiness
o Contribute to internal knowledge base, documentation, and methodology development
Requirement:
B.S/M.S in Microelectronics, Electronics, Electrical, Communication Engineering (or similar degree) with 3+ years of relevant industry experience.
Strong understanding of ASIC design flow, including parasitic extraction, post-layout simulation, and signoff methodologies.
Familiar with EDA tools such as Quantus/QRC, Virtuoso, or Innovus.
Strong debugging and problem-solving skills with the ability to analyze complex design behaviors.
Basic programming and scripting skills (e.g., Python, shell, or Tcl) with the ability to develop simple automation or data analysis scripts.
Experience in customer engagement, technical support, or cross-functional collaboration with AE/R&D teams is highly preferred.
Able to manage multiple tasks and priorities and work effectively in a fast-paced environment.
Strong communication and collaboration skills, with good English communication ability.
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
Offices: 2655 Seely Avenue, San Jose, California 95134, US
