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The candidate will perform physical layout for critical mixed-signal components and collaborate with design engineers to optimize performance and reliability. They are also responsible for floor planning, custom layout, and defining advanced verification methodologies for FinFET process technologies.
The role requires at least 10 years of hands-on analog/mixed-signal layout experience, with a minimum of 5 years specifically in FinFET nodes. Proficiency in Cadence custom layout tools and knowledge of DRC/LVS checking flows using Calibre are essential.
Transforming AI Architecture with Co-Packaged Optics
Ayar Labs is transforming AI infrastructure by accelerating data movement. Recognizing that the complexity and size of AI models are increasing at a rate that traditional interconnect technology cannot handle, the company has developed the industry’s first co-packaged optics (CPO) solution that enables customers to maximize the compute efficiency and performance of growing AI infrastructure, while reducing costs, latency and power consumption. Based on open standards and optimized for both AI training and inference, Ayar Labs’ optical I/O solution is backed by a robust ecosystem that enables it to integrate smoothly into AI systems at scale.
Offices: 695 River Oaks Pkwy, San Jose, California 95134, US · 5909 Christie Ave, Emeryville, California 94608, US · 678 Massachusetts Ave, Suite 401, Cambridge, Massachusetts 02139, US
