Director, Analog/Mixed Signal Design Location: San Jose, CA (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead …
Contract Sourcer Candidate must have worked for a semiconductor and/or optical communications company. Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (…
Contract Sourcer Candidate must have worked for a semiconductor and/or optical communications company. Location: Bangalore (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed…
Senior Staff Engineer, Silicon Validation Location: Bengaluru (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are us…
Sr. Staff Engineer, ASIC Physical Design Location: Bangalore (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are usi…
Skills: ASIC Physical Design, Synthesis, Place and Route, Static Timing Analysis, Physical Verification
Senior Engineer, Silicon Validation Location: Bengaluru (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using li…
Sr. Engineer, ASIC Physical Design Location: Bangalore (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using lig…
Skills: ASIC Physical Design, Synthesis, Place and Route, Static Timing Analysis, Physical Verification
Principal Engineer, Embedded Firmware Location: Bangaluru (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using …
Skills: Embedded Firmware, C Programming, Microcontrollers, SerDes, Photonics
Principal, ASIC Physical Design Location: Bangalore (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light …
Skills: ASIC Physical Design, Synthesis, Place and Route, Static Timing Analysis, Physical Verification
Principal Engineer, ASIC Design Verification Location: Bangalore (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are…
Contract Recruiter - Direct Sourcing (San Jose - onsite)
San Jose, California, United States · On-site
$45/hr–$55/hr
Mid level$875M raised
Contract Recruiter - Direct Sourcing Location: San Jose (hybrid) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of el…
Skills: Direct Sourcing, Boolean Search, X-ray Search, LinkedIn Recruiter, GitHub
Sr. Staff Engineer, Analog/Mixed Signal Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light in…
Skills: Analog Design, Mixed-Signal Design, Oscillators, High-Speed Transmitters, High-Speed Receivers
Principle Systems Reliability Engineer Location: San Jose , CA (On-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light inste…
Skills: System Reliability Engineering, Fleet Qualification, Test Infrastructure Design, Statistical Reliability Planning, Hardware Validation
Sr. Staff Engineer, Analog/Mixed Signal IC Layout Location: Bengaluru (on-site, hours flexible) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), w…
Skills: Analog IC Layout, Mixed-signal IC Layout, FinFET, Cadence, Calibre
Senior Engineer, Photonics Reliability Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of…
Sr. Staff Engineer, Front-End CAD / Design Automation Location: Bengaluru, India (on-site, flexible hours) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged opti…
Product Manager – CPO External Lightsources (ELS) Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light…
Sr Engineer: Silicon Validation Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electr…
Senior Payroll Analyst Location: San Jose, CA (onsite) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity …
Manager, Failure Analysis Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity …
Skills: Design for Reliability, Failure Mode and Effects Analysis, Physics-of-Failure Modeling, Wafer-Level Reliability, Root Cause Analysis
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$240k–$300k/yr
Full-time
bachelor degree, postgraduate degree
Posted 21h ago
~40 hrs/week
Responsibilities
The Director will lead the analog/mixed-signal design team to develop high-bandwidth optical links and manage the strategy for next-generation optical PHY products. They are responsible for driving architectural decisions, mentoring engineers, and ensuring successful silicon tapeouts through rigorous design methodologies.
Requirements
Candidates must hold a B.S. in Electrical Engineering and possess over 12 years of industry experience in analog/mixed-signal design. A proven track record of production tapeouts in advanced FinFET CMOS nodes is required.
Full job description
Director, Analog/Mixed Signal Design
Location: San Jose, CA (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
We are hiring a Director of Analog/Mixed Signal Design to lead the team responsible for the advanced circuits at the heart of our optical I/O products. You will own the analog/mixed-signal design strategy and execution for high-bandwidth optical links, including high-speed transmit and receive signal paths, clocking, data conversion, biasing, and power-management circuits. You will set clear technical direction, maintain a rigorous design methodology, and remove execution barriers, ensuring that the team delivers production-quality silicon on schedule.
Key Responsibilities
Drive architectural decisions for the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
Drive co-design efforts across the EIC/PIC boundary.
Lead the silicon-success methodology: first-silicon-success expectations, debug discipline, characterization-to-production.
Mentor AMS design engineers in design reviews and silicon debug.
Represent the AMS organization in cross-functional architecture reviews, customer technical engagements, and foundry/EDA partner discussions.
Manage and scale the design team to develop IP intercepting multiple parallel products.
Basic Qualifications
B.S. in Electrical Engineering
12+ years of industry experience in analog/mixed signal design
Track record of production tapeouts in advanced FinFET CMOS nodes
Demonstrated ability to deliver complex analog/mixed-signal IP across multiple concurrent programs.
Preferred Qualifications
M.S. or Ph.D in Electrical Engineering
Annual Salary Range: $240,000 - $300,000
NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
Transforming AI Architecture with Co-Packaged Optics
Industry
Computer Hardware Manufacturing
Company size
51-200 employees
Founded
2015
Headquarters
San Jose, California
LinkedIn followers
30,980
Total funding
$875M
Ayar Labs is transforming AI infrastructure by accelerating data movement. Recognizing that the complexity and size of AI models are increasing at a rate that traditional interconnect technology cannot handle, the company has developed the industry’s first co-packaged optics (CPO) solution that enables customers to maximize the compute efficiency and performance of growing AI infrastructure, while reducing costs, latency and power consumption. Based on open standards and optimized for both AI training and inference, Ayar Labs’ optical I/O solution is backed by a robust ecosystem that enables it to integrate smoothly into AI systems at scale.
Offices: 695 River Oaks Pkwy, San Jose, California 95134, US · 5909 Christie Ave, Emeryville, California 94608, US · 678 Massachusetts Ave, Suite 401, Cambridge, Massachusetts 02139, US
CPOPhotonicsand AI Scale-UpInformation TechnologySemiconductorOptical CommunicationHardwareArtificial Intelligence (AI)AI InfrastructureComputer
Transforming AI Architecture with Co-Packaged Optics
Industry
Computer Hardware Manufacturing
Company size
51-200 employees
Founded
2015
Headquarters
San Jose, California
LinkedIn followers
30,980
Total funding
$875M
Ayar Labs is transforming AI infrastructure by accelerating data movement. Recognizing that the complexity and size of AI models are increasing at a rate that traditional interconnect technology cannot handle, the company has developed the industry’s first co-packaged optics (CPO) solution that enables customers to maximize the compute efficiency and performance of growing AI infrastructure, while reducing costs, latency and power consumption. Based on open standards and optimized for both AI training and inference, Ayar Labs’ optical I/O solution is backed by a robust ecosystem that enables it to integrate smoothly into AI systems at scale.
Offices: 695 River Oaks Pkwy, San Jose, California 95134, US · 5909 Christie Ave, Emeryville, California 94608, US · 678 Massachusetts Ave, Suite 401, Cambridge, Massachusetts 02139, US
CPOPhotonicsand AI Scale-UpInformation TechnologySemiconductorOptical CommunicationHardwareArtificial Intelligence (AI)AI InfrastructureComputer