Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
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$207k–$230k/yr
Full-time
bachelor degree, postgraduate degree
Discretionary Bonus, Incentives
Posted 10d ago
~40 hrs/week
Responsibilities
Architect and implement UVM-based verification environments for high-speed SerDes/PHY IP to ensure first-pass silicon success. Collaborate with analog and digital teams to verify physical layer behavior against industry standards like PCIe and Ethernet.
Requirements
Requires a Bachelor's degree in Electrical or Computer Engineering and 8+ years of experience in high-speed SerDes or mixed-signal design verification. Expert proficiency in SystemVerilog, UVM, and experience with Real Number Modeling is essential.
Full job description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.
This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story. You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.
Key Responsibilities
Verification Architecture & Strategy
Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers
Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks
Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows
Execution & Coverage Closure
Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes
Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios
Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out
Physical Layer & Protocol Verification
Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards
Model and validate channel behavior, link training state machines, and analog handoff scenarios
Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks
Cross-Functional Leadership
Mentor junior DV engineers and set technical direction across the verification team
Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams
Contribute to verification IP reuse strategy and tooling improvements across product lines
Basic Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
Expert-level proficiency in SystemVerilog and UVM
Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL
Preferred Qualifications
MS or PhD in Electrical Engineering or Computer Engineering
Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
Scripting proficiency in Python or Perl for verification automation and regression management
Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results
Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment
Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Related keywords
SerDesPHYUVMSystemVerilogPCIe Gen 6PCIe Gen 7UALinkUCIeEthernetCXLNVLinkPMAPCSCDRCTLEDFE
AI Your Way. Purpose-built Rack-Scale Connectivity.
Industry
Semiconductor Manufacturing
Company size
501-1,000 employees
Founded
2017
Headquarters
San Jose, CA
LinkedIn followers
54,063
Total funding
$206M
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Offices: San Jose, CA, US · Toronto, CA · Taipei, TW · Shanghai, CN · Haifa, IL
Connectivity solutionsSignal ConditioningPCIeHeterogeneous ComputeHyper-scale Data CenterNVMeEthernetCXLAIML
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