Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Calendar management, Travel management, Expense reporting, Administrative support, Microsoft Outlook
Principal Design Verification Engineer- SerDes/PHY
San Jose, California, United States · On-site
$207k–$230k/yr
Senior+$206M raised
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Product Engineering, Test Engineering, ATE, Advantest 93k, Semiconductor Manufacturing
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Governance, Risk Management and Compliance, Senior Director
San Jose, California, United States · On-site
$225k–$250k/yr
Senior+$206M raised
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Signal Integrity, Power Integrity, Package Electrical Design, PCIe 5.0/6.0/7.0, CXL
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Sourcing, Procurement, Supplier management, Commercial negotiations, Manufacturing support
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Analog Layout, Mixed-Signal Design, Cadence Virtuoso, Synopsys, Mentor Graphics
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Physical design, Floorplanning, Placement, Clock tree synthesis, Routing
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Program management, Semiconductor development, Analog/Mixed-signal, ASIC development, Silicon validation
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Analog circuit design, Mixed-signal design, SerDes, PLL, Data converters
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
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$133k–$185k/yr
Full-time
bachelor degree, postgraduate degree
Discretionary bonus, Incentives
Posted 11h ago
~40 hrs/week
Responsibilities
The Principal Software Integration Engineer will own RTL design for assigned blocks from microarchitecture through synthesis sign-off. They will collaborate with cross-functional teams including architecture, verification, DFT, and physical design to ensure high-quality silicon delivery.
Requirements
Candidates must have a Bachelor's degree in Electrical or Computer Engineering and at least 5 years of digital design experience. Proficiency in Verilog/SystemVerilog and experience with high-speed serial interfaces like PCIe or Ethernet are required.
Full job description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is hiring a Principal Software Integration Engineer to help build and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.
This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.
Key Responsibilities
RTL Design & Implementation
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
Cross-Functional Execution
Partner with architecture to translate specifications into implementation-ready microarchitecture
Collaborate with verification on testplans, coverage closure, and bug triage
Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
Technical Leadership & Quality
Mentor junior engineers and contribute to design methodology, scripts, and best practices
Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
Drive structured, data-driven design decisions in support of aggressive tapeout schedules
Basic Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of digital design experience, including at least one full chip from spec to tapeout
Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
Hands-on experience with timing closure, CDC, lint, and low-power design techniques
Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
Preferred Qualifications
MS or PhD in Electrical Engineering or Computer Engineering
Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
Familiarity with formal verification, emulation, or assertion-based methodologies
Background in advanced process nodes (7nm, 5nm, or below)
Strong debug skills across pre-silicon and post-silicon environments
Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
AI Your Way. Purpose-built Rack-Scale Connectivity.
Industry
Semiconductor Manufacturing
Company size
501-1,000 employees
Founded
2017
Headquarters
San Jose, CA
LinkedIn followers
54,457
Total funding
$206M
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Offices: San Jose, CA, US · Toronto, CA · Taipei, TW · Shanghai, CN · Haifa, IL
Connectivity solutionsSignal ConditioningPCIeHeterogeneous ComputeHyper-scale Data CenterNVMeEthernetCXLAIML
AI Your Way. Purpose-built Rack-Scale Connectivity.
Industry
Semiconductor Manufacturing
Company size
501-1,000 employees
Founded
2017
Headquarters
San Jose, CA
LinkedIn followers
54,457
Total funding
$206M
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Offices: San Jose, CA, US · Toronto, CA · Taipei, TW · Shanghai, CN · Haifa, IL
Connectivity solutionsSignal ConditioningPCIeHeterogeneous ComputeHyper-scale Data CenterNVMeEthernetCXLAIML