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You will architect, design, and deliver high-performance analog and mixed-signal circuits for next-generation transceivers. Responsibilities also include silicon bring-up, debug, and supervising analog layouts within advanced process nodes.
Candidates must hold a Master's degree or PhD in Electrical Engineering with at least 5 years of relevant experience. Strong fundamentals in analog design and proficiency with industry-standard verification tools are required.
Are you an Analog Design Engineer passionate about building the high-speed interconnect technology powering the next generation of AI? Join our fast-growing semiconductor startup and help develop disruptive mixed-signal solutions that enable tomorrow's AI infrastructure. We are seeking experienced Analog Design Engineers to architect, design, and deliver high-performance analog and mixed-signal circuits for next-generation transceivers and other critical high-speed functions. This is an opportunity to work alongside a world-class engineering team, tackle challenging design problems in advanced process technologies, and make a direct impact on innovative products from architecture through silicon.
Locations: Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa, ON
What You Will Do:
• High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.)
• Clock generation and distribution (VCOs, PLL, clock distribution, etc.)
• Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc.)
• New techniques for the development of next generation optical transceiver
• Design of custom passive components, from concept to silicon implementation
• Supervise analog layouts within advanced process nodes
• System verification and circuit design spec creation
• Silicon bring-up, debug and support
• Team communication and documentation
What You Will Bring:
• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience
• Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE, and post layout extraction tools) is a must
• Experience in advance CMOS design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)
• Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus
• Knowledge of the fundamentals on electromagnetism, lump models, and high frequency design
• Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus
• Strong communication and documentation skills
Connecting AI at the Speed of Light
Celero Communications develops advanced coherent DSP solutions that enable high-bandwidth, low-power optical connectivity for AI infrastructure. Founded in 2024 by industry leaders from Marvell, Inphi, Broadcom, and ClariPhy, Celero combines deep expertise in analog design, digital signal processing, and system architecture to redefine how data centers connect and scale across large AI networks. The company is headquartered in Irvine, California, with design centers in Canada and Argentina.
Offices: 5281 California Ave, Suite 200, Irvine, CA 92617, US
