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$138k–$220k/yr
Full-time
bachelor degree
Medical Plan, Dental Plan, Vision Plan, 401(K) (USA), DCPP (Canada), Company Matching
Posted 27d ago
~40 hrs/week
Responsibilities
Lead the design and delivery of high-speed electrical transmitter macros for 224G and 448G SerDes in deep-submicron CMOS technologies. This includes owning the signal chain from schematic design through post-layout verification and collaborating with cross-functional teams for silicon validation.
Requirements
Requires a Bachelor's degree in Electrical or Computer Engineering and over 10 years of industrial experience in high-speed analog or SerDes transmitter circuits. Proficiency with Cadence, Mentor, or Synopsys tools and experience in full silicon delivery is essential.
Full job description
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
Ciena’sWaveLogicfamily of products enables high-speed optical transmission solutions that are foundational to modern telecommunications networks. This role contributes to the continued advancement of high-speed circuit design for broadband fiber-optic systems within avibrant team with a proven track-record of success over 30 years of evolution in high-speed circuits for broadband fiber-optic modems — the team that pioneered the world's first high-speed DAC and ADC analog macros for coherent fiber-optic products.
We are looking for a hands-on Transmitter (Tx) SerDes DesignLeadto design and deliver our high-speed electrical transmitter macros for 224G and 448G SerDes in the latest deep-submicron CMOS technologies.
How you will make an impact:
Own schematic-level design and post-layout verification of the transmitter signal chain andit’sblocks:DAC-based output stage, serialization, clocking interface, and output driver
Work closely with management, system designers, and lab validation teams to evolve the architecture and meet standard and product requirements
Evaluate circuit topologies and recommend implementations based ontradeoffsacross power, area, bandwidth, and technology constraints.
Collaborate with layout and design engineers to deliver designs through full GDSII integration.
Drive extraction-based post-layout simulations andvalidatetransmitterperformance(bandwidth, linearity/RLM, return loss, jitter, and power)across process, voltage, and temperature conditions.
Own root-cause analysis of design- and post-layout performance gaps and implement the corrective design actions to meet specifications.
Maintain block- and transmitter-level performance and power tracking against the agreed targets.
Translate agreed architecture and system requirements into the transmitterimplementation, andfeed design and silicon learnings back to inform the next architecture step.
Build and use behavioral/design models (e.g., MATLAB, Verilog-A) to support topology tradeoffs and specification alignment.
Partner with lab validation teams to correlate silicon results with simulations and supporttest-chip,product bring-upand characterization.
Provide technical guidance and mentorship to more junior design and layout engineers, and report status and share experience with the group on a regular basis.
The must haves:
Education:Bachelor’s degree in Electrical Engineering or Computer Engineering, or applicable scientific discipline.
Experience: 10+ years of industrial experience designing high-speed analog, mixed-signal, or SerDes transmitter circuits in advanced CMOS technologies, including schematic design through post-layout verification.
Application of transmitter circuit building blocks including DAC-based output stages, serializers or multiplexers, output drivers, and clocking circuits.
Execution of post-layout and extraction-based simulations tovalidateperformance across process, voltage, and temperature conditions.
Delivery of analog circuit designs through silicon validation.
Utilizationof Cadence, Mentor, or Synopsys tools including Virtuoso, Calibre, STAR-RC, and MMSIM.
Demonstrated written and verbal communication skills and ability to work independently and within a team environment.
Nice to haves:
Experience: Application of 224G or 448G PAM4 or PAM6 SerDes and related OIF-CEI or IEEE standards.
Experience contributing to transmitter architecture using MATLAB, Verilog-A, or C++.
Application of signal integrity, power integrity, channel, and package co-design methodologies, including use of EM tools such as HFSS or EMX.
Experience mentoring engineers within analog macro design teams.
Experience with mixed-signal validation using high-speed measurement and probing equipment.
Pay Range: The annual salary range for this position is $138,000 - $220,400 CAD.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
Ciena (NYSE:CIEN) is the global leader in high-speed connectivity. We build advanced networks to support exponential growth in bandwidth demand—empowering our customers, partners, and communities to thrive in the AI era. With unparalleled expertise and innovation, our networking systems, interconnects, automation software, and services revolutionize data transmission and network management.
Offices: 7035 Ridge Road, Hanover, Maryland 21076, US · 385 Terry Fox Dr, Ottawa, ON K2K 0L1, CA · 2351 Boulevard Alfred-Nobel, Montreal, QC H4S 2A9, CA · 505 Boulevard du Parc-Technologique, Québec, Quebec G1P 4S9, CA · 154 Middlesex Tpke, Burlington, Massachusetts 01803, US
Converged Packet-OpticalPacket Networking and Carrier EthernetOptical TransportSoftware and ServicesData Center InterconnectSoftware Defined Networking (SDN)Cloud NetworkingSubmarine Networkingand InternetOptical Communication
How many Engineering jobs are open in Ottawa, Canada right now?
There are currently 1,024 open engineering positions in Ottawa, Canada listed on Clera. New openings are added daily as companies post roles.
Which companies are hiring for Engineering roles in Ottawa, Canada?
Companies currently hiring include General Dynamics Mission Systems, uOttawa | Carrières - Careers, Ciena, City of Ottawa / Ville d’Ottawa, National Research Council Canada / Conseil national de recherches Canada, among others. Browse the listings above to see every active employer.
Are there remote or hybrid Engineering jobs in Ottawa, Canada?
Yes — 401 of the 1024 open engineering positions offer remote or hybrid work (60 remote, 341 hybrid).
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