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Full-time
bachelor degree, postgraduate degree
Posted 15d ago
~40 hrs/week
Responsibilities
The engineer will be responsible for chip-level and performance verification of custom ASICs. This includes designing end-to-end test flows and managing vendors or contractors to verify real-world performance scenarios.
Requirements
Candidates need a degree in Computer Science or Engineering and over 5 years of experience with UVM and constrained random verification. Proficiency in simulation tools like VCS and scripting languages such as Python or Perl is required.
Full job description
About Majestic Labs
We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training.
Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us!
About the position
We are looking for an experienced, highly skilled and motivated Pre-Silicon Verification Engineer to join our core team. In this role, you will be responsible for chip-level and performance verification of one of our custom ASICs.
Responsibilities
Work with our engineers and partners to help verify our ASICs
Work with our architecture team to understand our architecture and to design end-to-end test flows and methodologies to verify real-world performance scenarios
Manage vendors and/or contractors as necessary
Requirements
Bachelor’s or Master’s in Computer Science, Computer Engineering, or a related field from a recognized university
Expert-level experience with simulation tools & flows (VCS, Verdi, NCSim and the like)
Scripting experience in Perl and/or Python
5+ years experience using constrained random & functional coverage based verification methodologies on large design blocks
5+ years hands-on coding of UVM verification environments
C/C++ expertise is a plus
Excellent communication skills and a strong track record of cross-functional collaboration
Preferred Qualifications
Experience with and understanding of common LLMs
Experience with AI or other large-scale datacenter-grade ASICs
Experience doing performance verification of compute or networking ASICs
At Majestic Labs, we are shaping the next paradigm and making AI ubiquitous by building radically better infrastructure across the entire stack-from systems engineering and VLSI to compilers and AI applications. This epic mission requires a relentless culture of innovation, grit, and dedication. Our employees are our most important asset.
Have you read the job description and feel you could be a great fit?
We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges.
Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step-function shift in human technical capability-we want to meet you!
Majestic Labs is reimagining AI infrastructure for the world’s most demanding workloads. Today, organizations are forced to overprovision expensive compute just to access the required memory their models need. We took a fundamentally different approach by pairing a massive amount of compute with 1000x the memory to create game changing improvements in performance, power and deployment efficiency. Our customers can literally replace racks of traditional AI infrastructure with a single Majestic server.
AI InfrastructureSoftwareArtificial Intelligence (AI)AI Infrastructure
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