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The engineer will design and verify digital logic for thermodynamic hardware, owning the process from microarchitecture to tapeout. Responsibilities include writing synthesizable SystemVerilog, authoring verification environments, and collaborating with physical design teams for timing closure.
Candidates must have hands-on experience with production RTL in SystemVerilog and at least one successful silicon tapeout. Proficiency in verification tools like UVM or cocotb and the ability to work across design and verification disciplines are required.
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.
You will own RTL from microarchitecture to tapeout: writing synthesizable SystemVerilog, authoring verification environments in UVM, cocotb, or formal tools, and working closely with architecture and physical design to make sure what you build is both functionally correct and physically realizable. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.
This is a role for an engineer who does not draw a hard line between design and verification. The strongest candidates have taped out silicon, written both RTL and testbenches, and are comfortable working in an environment where the specification is still being developed in parallel.
RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
Verification: Author functional verification environments using UVM, cocotb, formal property checking, or a combination.
Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
Simulation Infrastructure: Develop and maintain simulation infrastructure, regression pipelines, and coverage closure flows.
Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.
Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
Experience authoring verification environments in UVM, cocotb, formal, or equivalent, not just running existing testbenches
At least one tapeout in your background, from any node and any company size
Comfort operating across both design and verification without treating them as separate disciplines
Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
Strong debugging instincts across simulation, waveforms, and formal counterexamples
Ability to work directly with architects and physical designers without needing a large intermediary layer
Industry experience in ASIC or SoC design
Experience at an AI chip company where design and verification were tightly coupled
Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
Familiarity with RISC-V or other open ISAs
Experience with AI-assisted RTL or EDA tooling in your design workflow
Exposure to physical design constraints, floorplanning, or timing-driven RTL development
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at [email protected].
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.
AI for our most pressing crises in silicon.
At Normal, we're rewriting AI foundations to advance the frontier of reasoning and reliability in the physical world. We are tackling problems across semiconductors and industrials with a mix of interdisciplinary approaches across the full stack: from probabilistic software infrastructure and algorithms to hardware and physics, enabling AI that can reason and understand its own limits. We understand that our technology is only as powerful as the people behind it. Every employee drives significant impact within our products, often working directly with customers and embedding across our tightly-knit team. Our team members are driven by curiosity and passion for solving some of the most challenging problems in the world of atoms. Normal was founded in 2022 by engineers and scientists that pioneered industry-leading Physics + ML tools for next-gen AI at Google Brain and Google X.
Offices: New York, NY, US · San Francisco, California, US · London, England, GB · Copenhagen, DK
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