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You will lead the development of performance and functional models for AI inference hardware, bridging the gap between software workloads and silicon architecture. This role involves hardware/software co-design, including tiling, ISA definition, and memory hierarchy analysis to ensure optimal performance and energy efficiency.
Candidates must have at least 8 years of experience in hardware or performance modeling with a strong background in computer architecture and AI accelerators. Proficiency in modern C++ and Python, along with experience in cycle-accurate simulation and workload analysis, is required.
The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape the future of computing!
Location: Austin, TX or Sunnyvale, CA. Full-time onsite position.
Reports To: Sr. Director of Modeling
FLSA Status: Exempt
We are seeking a staff-level modeling architect to build the path from a production model or application to two things: a performance and energy number Neurophos will stand behind, and a functional model that software can boot against before tape-out.
The T100 architecture is still moving, and the workloads are the models the industry is publishing now, so this is hardware/software co-design in practice. You will bind a workload to the programming model and runtime, run it on the model stack, and feed the result back into decisions on tiling, instruction set architecture (ISA), memory hierarchy, and multi-chip mapping. The team works between the principal architects, the RTL and physical design groups, and the compiler and runtime teams. At this level, you own a workload or block area along with the methodology behind it, and you mentor the engineers building models in that area.
Bring up inference workloads as they ship, including dense and Mixture of Experts (MoE) transformers, attention and KV cache, expert routing, quantization, and hybrid/SSM models, plus retrieval, speech, vision, and recommendation workloads where they map onto the accelerator.
Bind Hugging Face and PyTorch workloads to the programming model and runtime, then run them on the functional model so that software and architecture are looking at the same behavior.
Co-design tiling, scheduling, the instruction set architecture (ISA), the SRAM and High Bandwidth Memory (HBM) hierarchy, network-on-chip (NoC) traffic, and multi-chip mapping across pipeline, tensor, and sequence parallelism, including collectives.
Run roofline and limiter analysis and design space exploration across microarchitecture options, resolving bottlenecks between the compiler view and the hardware.
Develop Python energy and latency models in NumPy, Pandas, and Matplotlib that cover operators, tiling, SRAM and HBM traffic, and optical GEMM and vector-unit time.
Implement bit-accurate C++ functional models of optical GEMM, SRAM vector processors, dataflow engines, and HBM, including narrow arithmetic, so software can begin bring-up before tape-out.
Contribute to the C++ event-driven simulation kernel itself, including coroutines, timed components, and traces, rather than only calling into it.
Implement cycle-approximate and cycle-accurate performance, power, and area (PPA) models, and align them with RTL through Verilator, SystemVerilog, and co-simulation.
Keep numbers consistent across roofline, limiter, performance model, and RTL simulation of the same workload, and document where they disagree.
Set the modeling methodology for a workload area, deciding what gets modeled at which fidelity and how to arbitrate when models disagree.
Maintain the interface and register specs as the source of truth for generating the C++ and SystemVerilog views, and mentor the engineers building models in your area.
BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or equivalent practical experience.
8+ years of experience in hardware modeling, functional modeling, performance modeling, performance simulation, or accelerator performance analysis used by architects, RTL, compiler and runtime, or silicon teams. Graduate research may count toward this.
Track record of shipping a model or study that another team depended on, whether architecture, compiler, customer, or silicon.
Judgment to pick the right method for a given question among roofline, limiter analysis, analytical performance models, trace-driven simulation, transaction-level modeling (TLM), and RTL simulation.
Strong grounding in computer architecture, microarchitecture, memory systems, and AI accelerators, whether GPU, TPU, NPU, or custom SoC.
Modern C++ (C++17 or later) for functional models, performance models, and simulation infrastructure.
Python for models, analysis, and plots, including NumPy, Pandas, and Matplotlib.
Experience working inside a discrete-event, cycle-approximate, or cycle-accurate simulator such as SystemC, gem5, SST, or a custom kernel, rather than only driving one.
Ability to build an LLM or accelerator workload from a model card or paper, covering prefill and decode, MoE, GEMM tiling, and quantization.
PhD in Computer Engineering, Electrical Engineering, or Computer Science.
Hardware/software co-design alongside compiler, runtime, or ISA work, including MLIR, TVM, XLA, ONNX, operator fusion, or graph compilers.
Experience modifying or extending a simulation kernel, or correlating an analytical model against silicon, vendor datasheets, or measured datacenter GPUs and inference accelerators.
Familiarity with TLM 2.x, Verilator, SystemVerilog, DPI, or UVM.
Familiarity with HBM, DRAM controllers, cache, SRAM, network-on-chip (NoC), AXI, DMA, and scratchpad memory.
Power modeling with McPAT, CACTI, or a custom flow, plus FPGA prototyping or hardware emulation.
This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.
Join a team that invests in your future and your well-being. At Neurophos, we offer:
100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
Unlimited PTO. No rigid vacation banks, just a focus on delivery.
401(k) matching and stock option opportunities to ensure our success is your success.
Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.
Photonic ExaFLOPS AI chips
Neurophos is building AI inference chips that are two orders of magnitude faster and more energy-efficient than state-of-the-art GPUs. Its Optical Processing Unit uses a metasurface compute architecture with tunable optical elements roughly 10,000x smaller than conventional photonic approaches, delivering a step-change in compute density, speed, and power efficiency. This breakthrough targets the central constraint in AI infrastructure: manufacturing, powering, cooling, and deploying enough compute for hyperscale inference. By increasing compute per chip, per wafer, and per megawatt, Neurophos creates a fundamentally steeper scaling curve for AI. The company has strong strategic and commercial momentum. Microsoft engaged deeply and invested meaningfully in Neurophos’ 3x oversubscribed $110M Series A. Neurophos is engaged with most hyperscalers and has commercial negotiations underway. Neurophos has completed its first compute demonstration with a metasurface array and is taping out additional devices with improved reliability and performance. The company is working with the leading foundries, custom ASIC designers, optics suppliers, and packaging partners. Neurophos has tripled its headcount since closing its $110M Series A in January 2026, adding senior leaders from NVIDIA, Intel, Infinera, Qualcomm, Magic Leap, and other leading semiconductor and photonics companies.
Offices: Austin, Texas 78744, US · Sunnyvale, 94086, US
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