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Dallas, Texas, United States · On-site
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Austin, Texas, United States • On-site
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Lead the physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS process technology. Collaborate with cross-functional teams to ensure design convergence, integration, and productivity through automation scripts.
Requires a degree in Electrical Engineering or Computer Science with 5-10 years of professional experience in back-end physical design. Proficiency in RTL to GDS flows, scripting (Python, TCL, Perl), and industry-standard EDA tools is essential.
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
We are hiring for multiple office locations. This is a full-time, on-site role, and employees are expected to work at their designated team location. Relocation assistance is available for qualified candidates.
Key responsibilities include:
Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner
Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools
Work with RTL design teams to drive assembly and design closure.
Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes
Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
5+ years experience in back-end physical design
Expertise in full-chip & sub-hierarchy integration
Experience integrating and taping out large designs utilizing a digital design environment
Good understanding of RTL to GDS flows and methodology
Good scripting skills in Perl, tcl and Python
Good understanding of digital logic and computer architecture
Knowledge of Verilog
Good communication skills and self-discipline contributing in a team environment
Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous
Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous
Experience with multi-voltage and low-power design techniques is advantageous
Experience with Cadence Innovus is preferred
Expected Base Pay Range (USD)
132,500 - 196,140, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, we go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.
Offices: 5488 Marvell Lane, Santa Clara, CA 95054, US · 5th Floor, Block B Incubation Center Building, Lot D.01 Tan Thuan Road, Tan Thuan Export Processing Zone Tan Thuan Dong Ward District 7, Ho Chi Minh City, VN · 2 Temple Back East Temple Quay, Bristol , BS1 6EG, GB · 2Fl., No.1, Alley 20, Lane 407, Sec. 2 Ti-Ding Blvd., Nei Hu District, Taipei, Taiwan 114, R,O.C., TW · A-One Business Center Z.A. La Piece 1-A5, Rolle, 1180, CH
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