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$153k–$204k/yr
Full-time
bachelor degree, postgraduate degree
Competitive compensation, Collaborative work environment
Posted 24d ago
~40 hrs/week
Responsibilities
The role involves running RTL code through synthesis and place and route tools to create physical chip views. Responsibilities include analyzing performance via timing analysis and verifying power grids through EMIR analysis.
Requirements
Requires a degree in Electrical Engineering, Computer Engineering, or a related field. Experience with industry-standard EDA tools and block-level PNR for advanced CMOS nodes is considered a bonus.
Full job description
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.
What You Can Expect
In this onsite role, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
Every day you’ll be working hands-on by running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, then analyzing performance by running timing analysis and verifying the power grid by performing EMIR analysis, etc.
There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level and it’s your responsibility to review completed runs for errors or create optimizations from successful runs.
What We're Looking For
Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
Previous experience in Physical Design with a focus on block-level PNR for advanced CMOS process nodes is a bonus.
Working experience with industry-standard EDA tools for RTL Synthesis, Physical Design, Static Timing Analysis or Physical Verification is a bonus.
Enjoy learning by doing the work and having access to guides and a mentor.
Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before.
Good English both written and verbal.
Expected Base Pay Range
152,700 - 203,600, RON per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, we go all in with you.
Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.
Offices: 5488 Marvell Lane, Santa Clara, CA 95054, US · 5th Floor, Block B Incubation Center Building, Lot D.01 Tan Thuan Road, Tan Thuan Export Processing Zone Tan Thuan Dong Ward District 7, Ho Chi Minh City, VN · 2 Temple Back East Temple Quay, Bristol , BS1 6EG, GB · 2Fl., No.1, Alley 20, Lane 407, Sec. 2 Ti-Ding Blvd., Nei Hu District, Taipei, Taiwan 114, R,O.C., TW · A-One Business Center Z.A. La Piece 1-A5, Rolle, 1180, CH
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