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Skills: SystemVerilog, UVM, CPU verification, Computer architecture, Microarchitecture
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You will own the verification planning and execution for high-performance out-of-order CPU core units, including frontend, midcore, and load-store components. You will also collaborate with architecture and design teams to identify verification gaps, debug complex microarchitectural issues, and ensure signoff quality.
The role requires a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science. Candidates must have 5-8+ years of relevant experience in ASIC or CPU design verification with strong proficiency in SystemVerilog and UVM.
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
About the Role
SiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core units. This is a Staff individual-contributor role within the CPU Design Verification organization, aligned to high-performance core development.
This role spans key core areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch, and is aimed at engineers who can go beyond executing assigned tests to define strategy, identify verification gaps early, solve difficult microarchitectural problems, and raise the quality bar for the broader team.
You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly, risks are identified early, and signoff quality is achieved with strong technical judgment and scalable methodology.
Responsibilities
Own verification planning and execution for one or more high-performance out-of-order CPU core areas, with typical scope across Frontend, Midcore, Load-Store Unit, Hardware Prefetch, or related core-level interactions.
Drive block-level and core-level verification planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural behavior.
Define verification strategies for challenging behaviors such as instruction fetch, branch prediction, issue and dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification quality.
Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
Contribute reusable methodology, infrastructure, and technical guidance that improves productivity and verification quality across future core generations.
Minimum Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
Strong hands-on experience with SystemVerilog and UVM-based verification.
Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
Experience in one or more high-performance CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
Strong knowledge of verification flow methodology, including test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, and coverage closure.
Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
Preferred Qualifications
Experience with out-of-order core verification.
Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.
Experience collaborating with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
Experience mentoring engineers and influencing verification methodology beyond the immediate block or feature area.
Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.
What Success Looks Like
Verification plans capture the real architectural and microarchitectural risks early and completely.
Difficult CPU bugs are found early, debugged efficiently, and closed with durable solutions.
Coverage quality and testbench quality improve meaningfully under your ownership.
Architecture, design, and DV teams rely on you as a strong technical partner for difficult high-performance CPU verification challenges.
You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.
BS/MS Degree in EE, CE or CS
5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification
Deep understand of computer architecture is desired
Experienced developer using Object Oriented Programing principles
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
This position requires a successful background and reference checks and satisfactory proof of your right to work in
United States of AmericaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
Offices: 2625 Augustine Drive, Suite 101, Santa Clara, California 95054, US · 20 Station Road, Cambridge, England CB1 2JD, GB · 5001 Plaza on the Lake, Suite 310, Austin, Texas 78746, US · 2000 Hearst Avenue, Suite 400, Berkeley, California 94709, US · 33 Boston Post Rd West, Suite 170, Marlborough, Massachusetts 01752, US
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