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Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
Skills: Power Integrity, IR Drop Analysis, Electromigration Analysis, Cadence Voltus, Synopsys RedHawk-SC
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San Jose, California, United States · On-site
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San Jose, California, United States · On-site
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San Jose, California, United States • On-site
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Own and drive IR drop and electromigration (IR/EMIR) analysis and closure for the connectivity ASIC portfolio from floorplan to tapeout. Collaborate with cross-functional teams to ensure stable power delivery and meet foundry sign-off criteria.
Requires a Bachelor's degree in Electrical or Computer Engineering and 5+ years of experience in power integrity sign-off for complex SoCs at 7nm nodes and below. Proficiency in Cadence Voltus or Synopsys RedHawk-SC and scripting languages like Python or Tcl is essential.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is scaling the connectivity fabric behind the world's largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and electromigration (IR/EMIR) analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.
You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery, meet foundry sign-off criteria, and prevent long-term reliability issues in production silicon. This role is fully on-site at our San Jose, CA location.
Key Responsibilities
Basic Qualifications:
Preferred Qualifications:
Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
AI Your Way. Purpose-built Rack-Scale Connectivity.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Offices: San Jose, CA, US · Toronto, CA · Taipei, TW · Shanghai, CN · Haifa, IL
Based on 1153 listings with disclosed salaries, most software jobs in San Jose, CA pay between $125k–$290k per year. Individual offers vary with seniority, company size, and specialization.
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