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Full-time
bachelor degree
Medical Insurance, Dental Insurance, Vision Insurance, 401k With Matching Contributions, Short-Term Disability Insurance, Long-Term Disability Insurance
Posted 66d ago
~40 hrs/week
Responsibilities
Execute synthesis, PnR, and STA for ASIC chip partitions while ensuring adherence to strict schedules and design goals. Collaborate with architects and RTL designers to resolve implementation issues and drive physical verification signoff.
Requirements
Requires a Bachelor's degree in Electrical Engineering or a related field with over 7 years of hands-on experience in physical design. Proficiency in EDA tools like Innovus and Tempus, along with strong TCL scripting skills, is essential.
Full job description
Position:
Physical Design Engineer II (eInfochips Inc)
Job Description:
What You'll Be Doing:
Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.
What we are looking for:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
Preferred Qualifications:
7+ years of experience in physical design roles and related activities.
Proven ability to adhere to tight schedules and implement low-power design techniques.
Experience in System-on-Chip (SoC) design and implementation.
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.
What’s In It for You:
At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including various compensation plans and a solid benefits package.
Medical, Dental, Vision Insurance
401k, With Matching Contributions
Short-Term/Long-Term Disability Insurance
Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
Paid Time Off (including sick, holiday, vacation, etc.)
Tuition Reimbursement
Growth Opportunities
And more!
Arrangement Fully On-Site: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.
Location: Complete On-Site at San Jose, CA.
About eInfochips:
eInfochips, an Arrow company (Fortune #133), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries & verticals.
EEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy).
Location:
US-CA-San Jose, California (eInfochips)
Time Type:
Full time
Job Category:
Engineering Services
EEO Statement:
Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)
All Arrow job postings are for existing job vacancies. We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.
Arrow Electronics (NYSE:ARW) guides innovation forward for thousands of leading technology manufacturers and service providers. With 2025 sales of $30.9 billion, Arrow develops technology solutions that help improve business and daily life.
Our broad portfolio that spans the entire technology landscape, helps customers design, distribute and deploy forward-thinking products that make the benefits of technology accessible to as many people as possible. Learn more at arrow.com.
Are you thinking Five Years Out? Join us at careers.arrow.com.
Offices: 9201 East Dry Creek Road, Centennial, Colorado 80112, US · Frankfurter Straße 211, Neu-Isenburg, Hesse 63263, DE
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Based on 1749 listings with disclosed salaries, most software jobs in San Jose, CA pay between $120k–$286k per year. Individual offers vary with seniority, company size, and specialization.
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