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Lead the end-to-end architecture, microarchitecture, and RTL design of scalable Network on Chip (NoC) IP solutions for next-generation FPGA platforms. Collaborate with cross-functional teams to optimize interconnect solutions for power, performance, area, and reliability.
Requires a Bachelor's or Master's degree in Electrical or Computer Engineering with over 15 years of related experience. Must have 10+ years of expertise in System Verilog, NoC IP development, and various scripting languages.
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
As a Principal NoC IP Micro-Architect, you will be responsible for the end-to-end architecture, microarchitecture, RTL design, and technical leadership of scalable NoC IP solutions integrated into Altera's next-generation FPGA platforms. You will work closely with architecture, design, verification, software, physical design, and product teams to deliver high-performance interconnect solutions optimized for power, performance, area (PPA), scalability, and reliability.
This is a highly visible technical leadership role requiring deep expertise in SoC interconnect architectures, NoC fabrics, RTL development, performance modeling, and system-level optimization.
Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Creates prototypes, simulates models, and specifies systems requirements.
Prepares and designs logic diagrams and codes for implementing system design and test specifications.
Delivers software models for device level bring up, including user visible functionality, timing, and power.
Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
Strong understanding of the design methodology & advance EDA tools like timing constrains verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development as well as deploying automation & AI to enhanced the development efficiency.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
As a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $299,200 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
10 + years of experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis
10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script
10+ years of experience in FPGA design and programming is a plus.
10+ years of experience in RTL validation is a plus.
10+ years of experience in development of Network on Chip IPs.
5+ years of experience with the usage of AI with development process for high efficiency development would be a great plus.
Shaping the Future with Tech
Welcome to Altera, where digital transformation is at the heart of everything we do. We are a forward-thinking IT development company dedicated to helping businesses navigate and thrive in the digital age. Specializing in creating innovative solutions that drive efficiency, growth, and competitive advantage, we are your trusted partner in the journey toward digital excellence. At Altera, we understand that the digital landscape is constantly evolving, and so are the needs of your business. Our team of expert developers, designers, and strategists works closely with you to craft tailored solutions that align with your vision and goals. From custom software development to cutting-edge web and mobile applications, we empower your business with the tools and technologies needed to stay ahead in a rapidly changing world. Our approach is centered on collaboration and innovation. We take the time to understand your unique challenges and opportunities, delivering solutions that not only meet but exceed your expectations. With Altera, digital transformation is more than just a buzzword—it's a pathway to unlocking new possibilities and achieving sustainable success.
Offices: Gazapkhuli Street, N13, Tbilisi, GE
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