Meta is seeking a lead CAD and integration engineer to shape the methodology and physical implementation infrastructure for our custom silicon programs. Working at the intersection of circuit design, digital implementati…
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$178k–$250k/yr
Full-time
bachelor degree
Bonus, Equity, Health Insurance
Posted 4d ago
~40 hrs/week
Responsibilities
You will define and own the end-to-end digital implementation methodology, including RTL-to-GDS flows and physical signoff. Additionally, you will lead analog mixed-signal integration and develop automation frameworks to improve engineering productivity.
Requirements
Candidates must have a bachelor's degree and at least 8 years of industry experience in VLSI CAD or physical implementation. Proficiency in industry-standard EDA tools and scripting languages like Python, SKILL, or Tcl is required.
Full job description
Meta is seeking a lead CAD and integration engineer to shape the methodology and physical implementation infrastructure for our custom silicon programs. Working at the intersection of circuit design, digital implementation, and physical verification, you will define and own the CAD flows that take designs from RTL and schematic intent through to foundry-ready GDS deliverables. You will establish best practices across synthesis, place-and-route, analog mixed-signal integration, and physical signoff, while building automation frameworks and integrating AI-assisted design tools to accelerate engineering velocity across the silicon team.
Responsibilities
Define and own end-to-end digital implementation methodology including RTL-to-GDS flows, synthesis, place-and-route, DFT insertion, and multi-corner physical signoff
Lead analog mixed-signal physical integration strategy, establishing constraint authoring, floorplanning guidelines, and interface protocols between custom and digital domains
Develop and maintain CAD automation infrastructure using Python, SKILL, and Tcl to reduce manual effort across implementation, tapeout, and regression workflows
Integrate AI and LLM-assisted coding tools into CAD methodology to improve design automation productivity across the silicon engineering organization
Drive physical signoff convergence across timing, power, noise, and design rule checks to produce foundry-ready deliverables on schedule
Establish 3D integration and heterogeneous packaging flows including die-to-die interface planning, cross-die timing closure, and bump/interposer constraint management
Partner with foundry contacts on PDK qualification, design rule interpretation, and process design kit updates for leading-edge technology nodes
Define low-power implementation methodology including multi-voltage domain integration, UPF-based power intent authoring, and power analysis signoff
Provide technical direction to other engineers on CAD methodology decisions, flow architecture, and implementation best practices across multiple concurrent tapeout programs
Communicate implementation status, methodology decisions, and risk assessments to circuit designers, layout engineers, and program leadership
Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of industry experience in VLSI CAD, physical implementation, or silicon design methodology across multiple technology nodes and tapeouts
Expertise in full RTL-to-GDS digital implementation flows including synthesis, place-and-route, DFT, and multi-corner physical signoff using industry-standard EDA tools
Experience with analog mixed-signal physical integration including constraint authoring, floorplan coordination, and interface management between custom and digital design domains
Proficiency in scripting and automation using Python, SKILL, Tcl, or equivalent languages to build and maintain CAD flow infrastructure
Experience communicating methodology decisions, tapeout risk, and implementation status to cross-functional partners including circuit designers, layout engineers, and foundry contacts
Preferred Qualifications
Experience with 3D stacking or advanced packaging flows including die-to-die interface planning, cross-die timing analysis, and heterogeneous integration methodology
Experience with PDK qualification and design rule development in direct collaboration with foundry partners on leading-edge process nodes
Background in low-power design methodology including UPF-based power intent, multi-voltage domain integration, and power signoff for mobile or wearable silicon applications
Familiarity with AI-assisted design tools or LLM-based coding assistants applied to CAD automation or implementation flow development
$178,000/year to $250,000/year + bonus + equity + benefits
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Based on 2211 listings with disclosed salaries, most technology jobs in Sunnyvale, CA pay between $129k–$279k per year. Individual offers vary with seniority, company size, and specialization.
How many Technology jobs are open in Sunnyvale, CA right now?
There are currently 2,589 open technology positions in Sunnyvale, CA listed on Clera. New openings are added daily as companies post roles.
Which companies are hiring for Technology roles in Sunnyvale, CA?
Companies currently hiring include Google, Intuitive, Apple, Walmart, Wayve, among others. Browse the listings above to see every active employer.
Are there remote or hybrid Technology jobs in Sunnyvale, CA?
Yes — 743 of the 2589 open technology positions offer remote or hybrid work (55 remote, 688 hybrid).
How do I apply for Technology jobs in Sunnyvale, CA?
Each listing links directly to the employer's application page. Apply early — fresh listings get the most recruiter attention in the first two weeks.