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Full-time
bachelor degree
Posted 92d ago
~40 hrs/week
Responsibilities
Responsible for the timing closure of CPU projects and developing timing flows in collaboration with the CAD team. Works with micro-architects and implementation engineers to drive timing closure for the CPU.
Requirements
Requires a BS degree and over 10 years of industry experience with 1 GHz+ designs and static timing tools like Primetime or Tempus. Proficiency in scripting languages such as TCL, Perl, or Python is essential.
Full job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.
Description
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
• Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains
Experience with one of the following static timing tools: Primetime or Tempus
Experience with cross talk, noise, OCV, uncertainty, and derate methodology
Experience with script writing and debugging in one or more of the following languages: TCL, Perl, Python
Preferred Qualifications
Implementation experience on high performance CPU designs
Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
Knowledge of static timing tools and flows including how to handle multiple clock and power domains
Knowledge of device physics especially aspects which impact timing: cross talk, noise, OCV, uncertainty and derate methodology
Related keywords
CPU DesignTiming ClosureStatic Timing AnalysisPrimetimeTempusTCLPerlPythonCPU MicroarchitecturePhysical DesignSynthesisPlace & RouteLECDVSOCVCross Talk
We’re a diverse collective of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. And the same innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it. This is where your work can make a difference in people’s lives. Including your own.
Apple is an equal opportunity employer that is committed to inclusion and diversity. Visit apple.com/careers to learn more.
Offices: 1 Apple Park Way, Cupertino, California 95014, US
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