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You will own the end-to-end RTL design and microarchitecture of on-chip interconnect fabrics and high-speed I/O subsystems for production silicon. This involves collaborating with cross-functional teams to define specifications, implement AI-driven design flows, and ensure high-performance, deadlock-free communication across SoC agents.
Candidates must have at least 5 to 10+ years of experience in RTL design with a proven track record of advanced-node tapeouts involving NoC fabrics or high-speed I/O. A degree in Electrical or Computer Engineering is required, along with deep expertise in AMBA protocols, SystemVerilog, and SoC design methodologies.
Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads, and enable a new era of domain-specific chips that unlock capabilities impossible with current hardware paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel.
As a Founding Member of the Technical Staff on the RTL Design team at Architect, you’ll own the AI-driven microarchitecture and RTL design of the on-chip interconnect fabric and high-speed I/O data movement subsystems going into production silicon. You will define, drive, and revise the block-level micro-architecture specification for NoC routers, crossbar switches, high-speed fabric bridges, and peer-to-peer data transfer engines — ensuring low-latency, high-bandwidth, and deadlock-free communication across all SoC agents.
Own the on-chip fabric RTL end-to-end: from NoC topology and router microarchitecture through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow.
Design and implement AMBA-based interconnect fabrics: including AXI/ACE/CHI-compliant crossbar switches, network interfaces (NIs), protocol converters (AXI-to-CHI bridges, AXI-to-AHB/APB downconverters), and multi-layer interconnect configurations optimized for ML accelerator traffic patterns.
Architect NoC routers and topologies: including virtual-channel routers, wormhole/flit-based switching, adaptive routing algorithms, QoS-aware arbitration (bandwidth regulation, latency-critical path prioritization), and deadlock-free network design for mesh/ring/tree topologies.
Design high-speed I/O fabric bridges and peer-to-peer engines: including PCIe/CXL-to-fabric bridges, chip-to-chip interconnect logic (UCIe, custom die-to-die links), peer-to-peer DMA controllers for direct device-to-device transfers bypassing host memory, and coherent/non-coherent multi-chip fabric extensions.
Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (latency vs. bandwidth vs. area, coherence overhead vs. performance), and feed area/timing/power realities back into the architecture and internal AI systems.
Define and maintain interface specifications: AMBA AXI4/AXI5, ACE/ACE-Lite, CHI (with snoop filter interfaces), AXI-Stream for streaming datapaths, custom sideband channels for QoS/ordering, and high-speed SerDes-facing interfaces for off-chip links.
Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, NoC configuration generators, regression flows, lint/CDC waivers, and integration collateral for the interconnect subsystem.
Close collaboration with DV: Support verification bring-up with interconnect reference models, protocol compliance checkers (AXI/CHI protocol monitors), SVA assertions for ordering rules and deadlock freedom, coverage plans targeting corner-case traffic scenarios (multi-master contention, QoS starvation), and architectural documentation for verification closure.
Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your interconnect domain expertise — particularly around traffic modeling and fabric configuration optimization.
Support FPGA prototyping on Xilinx for early functional validation of the fabric, including multi-master traffic generation and performance characterization on FPGA platforms.
Degree: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
Experience: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.
AMBA Protocol Expertise: Deep familiarity with ARM AMBA protocol suite — AXI4/AXI5 (channel mechanics, burst types, ordering, exclusive access), ACE/ACE-Lite (coherence transactions, snoop channels), CHI (request/response/data/snoop flits, home nodes, snoop filters), and legacy AHB/APB for peripheral integration.
NoC/Fabric Design: Hands-on experience designing or owning crossbar switches, NoC routers, or multi-layer interconnects including arbitration schemes (round-robin, priority, age-based, bandwidth-regulated), virtual channel management, flow control (credit-based, ready/valid), and QoS mechanisms.
High-Speed I/O Integration: Experience with HSIO bridge logic — PCIe root complex/endpoint bridge design, CXL.io/CXL.mem/CXL.cache protocol translation, or custom chip-to-chip links (UCIe, proprietary die-to-die) including link-layer protocols, credit management, and replay/retry logic.
Peer-to-Peer Data Movement: Experience with peer-to-peer DMA architectures, zero-copy data transfer engines, scatter-gather descriptors, and direct device-to-device communication paths that bypass host memory bottlenecks.
SystemVerilog: Clear, synthesizable, lint-clean RTL with strong design habits — parameterization for configurable port counts and data widths, modularity for hierarchical fabric composition, and configurability for different topology and QoS instantiations.
SoC Methodology: Solid grasp of synthesis, timing constraints (especially for wide crossbar paths and high-radix switches), clock domain crossings (fabric-to-IP clock boundaries, async bridge design), reset strategies, and power management for interconnect logic.
Python: Strong skills for design automation, traffic generation/analysis, NoC configuration scripting, regression infrastructure, and tooling.
PPA Ownership: Experience taking an interconnect or fabric block from RTL through synthesis and working with PD teams on timing/area/power closure — particularly for wide-datapath crossbars and high-frequency router pipelines.
Experience with coherent multi-chip/multi-die interconnect architectures (chiplet-based designs, UCIe, BoW).
Familiarity with hardware coherence protocols: MOESI/MESIF state machines, snoop filter design, directory-based coherence.
Experience with network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis.
Low-power design techniques for interconnect: clock gating idle ports, power gating unused links, link-level power states (L0s/L1), dynamic frequency/width scaling.
FPGA prototyping experience (Xilinx Vivado/Vitis), especially with AXI interconnect IPs, NoC IPs (Versal), or custom fabric implementations.
SVA assertions for protocol compliance: AXI ordering rules, CHI transaction flows, deadlock detection, and livelock/starvation monitors.
Prior IP building and delivery experience for NoC IPs, AXI interconnect IPs, PCIe controllers, or CXL endpoint/switch IPs.
Performance modeling: experience building or using NoC simulators (e.g., BookSim, Garnet) or system-level traffic models to validate fabric microarchitecture.
Domain-specific research contributions: publications or patents in on-chip networks, interconnect architectures, or high-performance data movement for ML/HPC workloads.
You’ll join a founding team building the future of chip design at the intersection of AI and silicon. Your interconnect and fabric expertise will directly shape the communication backbone of production ASICs — enabling the data movement performance that ML workloads demand — and influence how AI transforms hardware development from spec to tapeout.
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