Engineering Jobs in Bengaluru, India (Now Hiring) — 15,240 open — Page 718

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
• 4 years of experience in DFT specification definition architecture and insertion.
  
• Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and verification flow.
• Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging Automatic Test Pattern Generation (ATPG) patterns, compressed ATPG patterns, Memory Built-In Self-Test (MBIST) and Joint Test Action Group (JTAG) related issues.
• Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
  
• Experience with silicon bring-up, ATE pattern debug, and failure analysis (diagnosis) to support yield improvement.
• Experience in multi-voltage, and multi-clock domain SoCs.
• Familiarity with generating and validating patterns for High-Speed I/Os (HSIO) and analog/mixed-signal IPs.
• Proficiency with a scripting language like Perl, Tcl or Python.

About the job:

In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.

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Responsibilities:

• Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team.
• Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, path delay, and IDDQ) for Automated Test Equipment (ATE), while actively managing pattern volume and test time reduction (TTR) strategies.
• Develop and verify specialized test sequences and parametric measurement patterns to validate and characterize analog IPs (PLLs, LDOs, ADCs) and high-speed I/Os (SerDes, DDR, PCIe, MIPI).
• Partner closely with the Product Engineering teams to validate patterns on silicon, lead the diagnosis of ATE failures, and perform root-cause analysis to support yield learning and rapid ramp-to-production.
• Enhance DFT flows and methodologies using scripting (Tcl, Perl, Python) to automate insertion and validation processes, ensuring a correct-by-construction approach for future SoC.