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Full-time
bachelor degree
Posted 18d ago
~40 hrs/week
Responsibilities
You will be responsible for building and maintaining Palladium emulation environments and performing system-level debug of complex hardware issues. Additionally, you will develop automation scripts to improve build efficiency and collaborate with multi-disciplinary teams to ensure project milestones are met.
Requirements
The role requires a Bachelor's degree and a minimum of 10 years of relevant industry experience. Candidates must possess strong expertise in emulation platforms like Cadence Palladium, proficiency in debug methodologies, and a solid understanding of SoC architectures and RTL design.
Full job description
As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs.
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
In this role, you'll be responsible for the following:
- Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
- System-level debug and root cause analysis of complex hardware issues on the emulation platform.
- IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
- Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
- Performance profiling and optimization of emulation models to maximize execution speed.
- Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience
Preferred Qualifications
Proven experience with Cadence Palladium (or equivalent emulation platforms such as Synopsys ZeBu), including build flows, compile optimization, and platform bring-up
Strong debugging skills with experience in system-level and IP-level debug on emulation platforms
Experience with emulation compile flows, including synthesis for emulation, memory compilation, clock modeling, and I/O abstraction
Proficiency in debug tools and methodologies (waveform analysis, signal probing, assertion-based debug, transactors)
Solid understanding of RTL design concepts, SoC architectures, ARM-based subsystems, and standard bus protocols (AXI, AHB, APB)
Experience developing and maintaining automation scripts (Python, Tcl, Perl, Shell) to streamline emulation workflows
Strong analytical and problem-solving skills with ability to debug complex system-level issues
Experience with Wireless SoC applications (Wi-Fi, Bluetooth, cellular) - strongly preferred
Excellent communication and collaboration skills to work effectively across functional teams
Experience with version control systems (Git, Perforce) and CI/CD integration for emulation flows
Related keywords
Silicon ValidationEmulationSoCWirelessHardware AcceleratorsARMCadence PalladiumRTLVerificationTape-outNetlistMemory ModelingRoot Cause AnalysisAutomationPythonTcl
We’re a diverse collective of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. And the same innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it. This is where your work can make a difference in people’s lives. Including your own.
Apple is an equal opportunity employer that is committed to inclusion and diversity. Visit apple.com/careers to learn more.
Offices: 1 Apple Park Way, Cupertino, California 95014, US
Based on 2198 listings with disclosed salaries, most technology jobs in Sunnyvale, CA pay between $130k–$280k per year. Individual offers vary with seniority, company size, and specialization.
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