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Verify circuitry for semiconductor chips using System Verilog and Synopsys VCS to ensure designs meet customer specifications. Collaborate with RTL and DFT engineers and present test plans for larger blocks to review committees.
Requires a Bachelor's in Electrical or Computer Engineering with 2-3 years of experience, or a Master's/PhD in the same fields. Must be proficient in Verilog, Python, and Linux, with a strong background in VLSI and chip design.
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
In this in-office role in Santa Clara , you’ll work day to day with an RTL engineer to verify their design. Their design is in Verilog; you’ll use System Verilog to debug. You’ll run simulations using Synopsys VCS or a similar program, and then debug as needed until the design meets required specifications. You’ll also work closely with DFT engineers who are working in parallel on your blocks.
You’ll attend weekly staff meetings to go over what everyone is working on and update your progress or address any issues. As you take responsibility for larger blocks, you may have to present to a review committee and explain your test plan and test schedule for those larger blocks.
To be successful in this role you must:
- Have completed a Bachelor’s Degree in Electrical Engineering or Computer Engineering and have 2 to 3 years of related professional experience OR a Master’s Degree and/or PhD in those fields.
- Your coursework must have included some analog classes, Verilog or VHDL, basic circuits, and computer architecture. You should have a focus in VLSI or show projects in your courses that directly relate to chip design.
- You have used a tool like Synopsys, Cadence, or Mentor to run simulations and you can write and debug a testbench.
- Be comfortable working in a Linux environment and doing scripting with Python.
- Be extremely detail-oriented and ready to iterate a design over and over again until it is refined completely.
- Work and communicate well with your team, keeping them in the loop about your progress, issues you encounter, and any deviations from the planned schedule.
Expected Base Pay Range (USD)
96,570 - 144,600, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, we go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.
Offices: 5488 Marvell Lane, Santa Clara, CA 95054, US · 5th Floor, Block B Incubation Center Building, Lot D.01 Tan Thuan Road, Tan Thuan Export Processing Zone Tan Thuan Dong Ward District 7, Ho Chi Minh City, VN · 2 Temple Back East Temple Quay, Bristol , BS1 6EG, GB · 2Fl., No.1, Alley 20, Lane 407, Sec. 2 Ti-Ding Blvd., Nei Hu District, Taipei, Taiwan 114, R,O.C., TW · A-One Business Center Z.A. La Piece 1-A5, Rolle, 1180, CH
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