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Full-time
bachelor degree, postgraduate degree
Posted 26d ago
~40 hrs/week
Responsibilities
You will lead the DFT strategy, architecture, and implementation for complex SoCs from RTL to silicon bring-up. This includes managing ATPG pattern generation, memory repair solutions, and driving silicon validation and yield improvement.
Requirements
Candidates must have a bachelor's or master's degree in Electrical or Electronics Engineering with over 8 years of hands-on DFT experience. Expert-level proficiency in industry-standard EDA tools and a proven track record in silicon bring-up and post-silicon debug are required.
Full job description
Role Overview
We are hiring a Staff DFT Engineer to lead DFT strategy, architecture, and implementation for complex, high-performance SoCs. You will define methodologies, and drive DFT from RTL to silicon bring-up, ensuring optimal quality, cost, and time-to-market.
WhatYou’llDo
Define DFT architecture and test strategy for SoCs, including scan, compression, MBIST, LBIST, and IO test.
Lead ATPG pattern generation, optimization, and diagnosis flows across multiple fault models.
Architect and oversee MBIST, BISR, and memory repair solutions for large memory arrays.
Design and implement advanced test access mechanisms using JTAG, Boundary Scan (BSCAN), and IJTAG (IEEE 1687).
Drive DFT timing closure, power-aware DFT, and hierarchical/multi-core test strategies.
Own pre-silicon DFT verification (ATPG simulation, GLS) and coverage closure.
Lead silicon bring-up, ATE test program development, post-silicon validation, debug, and yield improvement.
Collaborate with cross-functional teams to integrate DFT into the overall design flow and resolve complex issues.
Mentor junior and mid-level engineers; contribute to methodology development and tool evaluation.
Optimize test time, data volume, and manufacturing test costs.
What We’re Looking For
Bachelor’s/master’s degree in Electronics/Electrical Engineering.
8+ years of strong hands-on experience in DFT for complex SoC/ASIC projects.
Expert-level knowledge of ATPG, MBIST, LBIST, IJTAG, BSCAN, scan compression, and related areas.
Proven track record in silicon bring-up, ATE support, and post-silicon debug.
Deep understanding of full ASIC flow (RTL to Silicon) and DFT impact on PPA.
Proficiency with leading EDA tools (Synopsys TetraMAX/DFTMAX, Siemens/Tessent SSN, TestKompress etc.).
Strong scripting and automation skills.
Good To Have
Knowledge of advanced topics like 2.5D/3D packaging test, analog/mixed-signal DFT.
AI silicon doesn't fail on compute. It fails on the infrastructure around it — power delivery, connectivity, and memory that weren't designed for the scale, speed, and packaging requirements of modern AI systems.
TYLsemi builds the chiplet infrastructure layer that solves this. Purpose-built for XPUs and Networking. Standards-based. Designed to integrate directly into your silicon program — not adapted from something else.
We're hiring across the US and India. Come build what's missing.
https://www.tylsemi.ai/company/careers/
Offices: San Jose, California, US · Bangalore, IN
semiconductorscustom siliconchipletsUCIeadvanced packagingXPUPower DeliveryConnectivityand AI Infrastructure
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