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Debug Lead Engineer

 

Roles & Responsibilities for Lead System Engineer:  

1. Assume technical responsibility from Pre-silicon to Post-silicon environment for Feature enablement and SoC-System level flow for use cases. 
2. Pre-Silicon: New SOC features enablement, implementation and coverage plan in Emulation 
3. Pre-silicon: Review all Silicon bugs that deferred out SOC Tape out and ensure it does not impact the system level features / use cases. 
4. Post Silicon: Lead the Bring-up planning in collaboration with Silicon teams, Platform, Firmware / BIOS, Post Si Validation team so we have the fastest and functional bring-up as soon as silicon arrives in the lab. 
5. Post Silicon: Partner with SOC NPI PM and be the technical lead to support & debug SOC related challenges from Tape out all the way to SOC IP milestone.  
6. Post Silicon: Lead cross-functional critical silicon issue debug, uplevel and communicate the updates into core teams and Management program reviews. 
7. Post Silicon: Provide inputs to Silicon Validation teams on coverage for New SOC features, enablement, implementation, IPs, and functional coverage at the system level. 
8. Exhibit strong technical leadership on X86 architecture and associated feature implementation 
9. Exhibit great technical depth in the post silicon enablement and validation of both HW and FW aspects to take the right technical decisions for the team 

 

Individual requirements: 

1. Highly skilled engineering professional with over 15 years of experience.

1. Solid experience in both Pre and Post Silicon enablement and validation with strong BIOS/FW/SW intercepting knowledge. 

1. Solid Experience and Knowledge in the HW and FW aspects of X86 design 
2. Solid experience in connecting the bigger picture across different related domains between Hardware/Firmware and Software and com 
3. Adept in calling out risks while anticipating issues and coming up with appropriate mitigation plans 
4. Experienced in working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders and create a robust alignment setup while running execution. 
5. Preferred experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW. 
6. Experience in High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects. 
7. Experience in Power Management 
8. Hands-on high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc. 
9. Preferred experience with scripting using TCL, Python 
10. Excellent communication, collaboration, articulation, upleveling to senior management and team playing skills. 

 

Key responsibilities: 

1. Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts. 
2. Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path. 
3. Be on top of all issues pertinent to Debug & Triage of any functional issues across the entire validation cycle  
4. Drive meetings for issue closures and actively track schedules and milestone quality metrics 
5. Ensure the Best-in-class Documentation and collateral delivery from the team. 

 

#L1-RG2

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

 

This posting is for an existing vacancy.