San Jose, California, United States · On-site
ABOUT LUMILENS At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new…
Skills: Physical Design, RTL to GDSII, Floorplanning, CTS, Routing
San Jose, California, United States · On-site
$130k–$175k/yr
Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. …
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San Jose, California, United States · On-site
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Sierra Circuits is a Silicon Valley-based leader in printed circuit board manufacturing and assembly, specializing in high-quality, quick-turn and complex prototypes. With over 35 years of experience, Sierra provides a s…
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San Jose, California, United States · On-site
The optometrist will conduct eye exams for Acuity Eyecare group and strive to practice to the full capacity of their license. The optometrist will support practice growth by establishing patient relationships and educati…
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San Jose, California, United States · On-site
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Team Credo is looking for a PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of adva…
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San Jose, California, United States · On-site
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San Jose, California, United States · Remote OK
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San Jose, California, United States · On-site
ABOUT LUMILENS At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new…
Skills: III-V Etching, Semiconductor Fabrication, Process Development, DOE Design, Metrology
San Jose, California, United States · On-site
$151k–$219k/yr
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San Jose, California, United States · On-site
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview The Director of System Engineering & Integration leads the definition, architecture, and exe…
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San Jose, California, United States · On-site
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Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four …
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San Jose, California, United States · Hybrid
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About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and…
Skills: Analog Circuitry, Control Theory, PCB Layout, Circuit Design, Hardware Testing
San Jose, California, United States · On-site
Company Description 1 Yr Contract Onsite Mid- Level Pay Rate: ~$13,975/mo DOE We are looking for a highly motivated AI Full Stack Developer to join our team to build, deploy, and maintain end-to-end applications that lev…
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San Jose, California, United States · On-site
$75k–$100k/yr
Company Description WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made acce…
Skills: HDD Teardown, Failure Analysis, Clean Room Procedures, Electrical Failure Analysis, Materials Characterization
San Jose, California, United States · On-site
$75k–$100k/yr
Company Description WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made acce…
Skills: Failure Analysis, Reliability Integration, Data Analysis, Root Cause Determination, Electronics Testing
San Jose, California, United States · On-site
Speech and Language Pathologist Join Our Team as a Speech Therapist / Speech-Language Pathologist (SLP) Direct Hire: New graduates are welcome to apply!! Make a Real Difference in Rehabilitation Be Part of Our Team: Full…
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San Jose, California, United States · Hybrid
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San Jose, California, United States · On-site
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Overview The Sigrity R&D team is seeking a highly skilled and motivated Software Engineer to help drive i…
Skills: C++, Computational Electromagnetics, Circuit Theory, Electromagnetic Field Solvers, Signal Integrity
San Jose, California, United States · Hybrid
$116k–$193k/yr
Work Flexibility: Hybrid The Team Leader, Test role combines hands-on individual contributor responsibilities with direct people management of Test Engineers for the Surgical Support portfolio within the Endoscopy Busine…
Skills: Verification Strategy, Test Method Development, People Management, Risk Mitigation, Technical Problem Solving
San Jose, California, United States · On-site
$62/hr–$120/hr
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into inte…
Skills: Semiconductor Layout Design, Cadence Virtuoso, Synopsys, Calibre, Physical Verification
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Own the full-chip and block-level physical implementation from RTL to GDSII for high-performance ASICs. Drive timing, power, and area closure while performing tapeout signoff activities in advanced TSMC nodes.
Requires a Bachelor's or Master's degree in Electrical Engineering and 8+ years of physical design experience, specifically with 5nm nodes or below. Proficiency with industry-standard tools like ICC2 and Innovus, along with scripting skills, is essential.
At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.
We’re a well-funded startup backed by Mayfield and led by veterans who’ve built
And scaled some of the most transformative technologies in the industry. This isn’t
incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from
the silicon up. You’ll work alongside a team of world-class engineers solving some of
the hardest challenges in optics, systems, and scale. Every line of code, every design
decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.
If you're looking for mission, momentum, and the chance to make an outsized impact
jump on the rocket ship. We’re just getting started.
We are seeking a Senior Physical Design Engineer to join our silicon design team developing high-performance ASIC using TSMC advance process nodes, including 5nm and 3nm. In this role, you will own physical implementation from RTL to GDSII, drive timing and power closure for ultra-high-speed designs, and work closely with RTL, STA, IP, and verification teams to solve complex implementation challenges unique to advanced-node and high-speed transceiver architectures.
Physical Implementation: Own full-chip and block-level physical implementation, including floorplanning, placement, CTS, routing, and physical verification for high-speed designs in advanced TSMC nodes.
Timing, Power, and Area Closure: Collaborate closely with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power closure across complex design blocks and full chip.
Advanced Physical Design: Apply physical design techniques for multi-voltage and multi-frequency domains, hierarchical implementation, physical-aware synthesis, congestion mitigation, skew optimization, and RC extraction-aware placement and routing.
Signoff and Tape out: Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry-standard verification tools.
Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
Experience: 8+ years of hands-on physical design experience, preferably with advanced technology nodes at 5nm or below.
Physical Design Expertise: Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, timing closure, and signoff debugging.
Tools and Automation: Hands-on experience with tools such as Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Simens Calibre etc, along with strong scripting skills in Tcl, Python, or Perl.
High-Speed PHY Implementation: Experience with high-speed PHY such as SerDes, UCIe etc physical design implementation.
Advanced-Node Signoff: Familiarity with EM/IR analysis, power grid optimization, congestion analysis, physical verification, and tapeout signoff in advanced semiconductor process nodes.
High-Frequency Design Exposure: Experience supporting high-frequency datapath or DSP-heavy designs is a plus.
2.5D or 3D design experience: Experience with TSMC CoWoS or SoIC-X design experience is a strong plus.
What we offer
Competitive salary commensurate with experience
Comprehensive benefits package including health insurance
Professional development opportunities and certification support
Access to cutting-edge technology and cloud platforms
Collaborative work environment with cross-functional teams
*Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.
The Connectivity Platform for AI
Lumilens addresses the red hot market for AI data center infrastructure by designing, manufacturing and selling photonic interconnect solutions. We design and use custom robotics + AI in our factories to more efficiently build our products. Lumilens is backed by top-tier venture capital investors including Mayfield and Spark Capital.
Offices: 2570 N 1st St, Suite 300, San Jose, California 95131, US
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