Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the fu…
About the role We are seeking a Senior Technical Project Manager (TPM) to drive cross-functional planning and execution for our Software programs. In this role, you will work closely with engineering leaders across softw…
Skills: Technical program management, Software development lifecycle, Cross-functional coordination, Project scheduling, Risk management
Manufacturing Associate II - Swing Shift Mon-Fri (1pm-9:30pm) *PC 570
San Jose, California, United States · On-site
$27/hr–$32/hr
Mid level
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Teamwork makes the stream work. Roku is changing how the world watches TV Roku is the #1 TV streaming platform in the U.S., Canada, and Mexico, and we've set our sights on powering every television in the world. Roku pio…
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Mammography Technologist and Breast Sonographer PRN
San Jose, California, United States · On-site
$35/hr–$54/hr
Mid level$2M raised
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About the role Muon seeks a Satellite Operator to join our Operations team in San Jose, CA. You will be at the forefront of our satellite and specialty sensing operations, ensuring the seamless functioning, monitoring, a…
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Skills: Hardware reliability, Test engineering, Spacecraft qualification, Team leadership, Reliability modeling
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About the role Muon Space is seeking an experienced and hands-on Senior Electrical Test Engineer to join our team in San Jose, CA. In this role, you will own the architecture, development, and scaling of the test infrast…
Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Toget…
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Cover
RF and Microwave Engineer
San Jose, California, United States · On-site
$150k–$350k/yr
Senior
Cover is an AI security company developing concealed weapon detection systems. Cover’s imaging technology scans students for concealed weapons in K-12 schools in the United States. Our goal is to deter school shootings b…
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Company Description Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, Califor…
Skills: NAND memory, Semiconductor device physics, Data analysis, C, C++
Company Description Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, Califor…
Company Description Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, Califor…
Skills: NAND device physics, Data analysis, Semiconductor memory, C, C++
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$185k–$240k/yr
Full-time
bachelor degree, postgraduate degree
Discretionary Bonus, Incentives, Benefits
Posted 14d ago
~40 hrs/week
Responsibilities
Define and maintain reusable physical design flows and automation infrastructure to scale the team's capabilities. Own the end-to-end RTL-to-GDSII flow across multi-vendor toolchains to improve PPA and schedule predictability.
Requirements
Requires a Bachelor's degree in Electrical or Computer Engineering and 8+ years of experience in physical design methodology for complex SoCs at 7nm and below. Expert-level scripting skills in Python, Tcl, or Perl and proficiency with Cadence and Synopsys toolchains are essential.
Full job description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
As a Principal Physical Design Engineer - Methodology, you will define, develop, and maintain the reusable physical design flows and automation infrastructure that the entire PD team relies on. You will build the RTL-to-GDSII flow, integrate and qualify tools from multiple vendors (Cadence and Synopsys), and continuously improve PPA and schedule predictability across all programs. You are the force multiplier scaling the team's capabilities and enabling faster, better tapeouts. This role is fully on-site at our San Jose, CA location.
Key Responsibilities:
Flow & Methodology Ownership
Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR
Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus; Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC)
Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability
Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements
Automation & Scale
Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage
Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs
Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization
Standards, Quality & Enablement
Establish best practices, runset standards, and quality checks that scale across multiple concurrent tapeout programs
Support physical design engineers with flow issues, tool configurations, and methodology guidance
Drive adoption of flow improvements across the team, including training and documentation
Basic Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Masters Preferred.
8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below)
Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows
Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains
Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation
Experience building and maintaining multi-corner/multi-mode analysis infrastructure
Understanding of foundry design rules, technology files, and enablement kit integration
Ability to work independently with strong prioritization and a results-driven mindset
Preferred Qualifications:
Knowledge of agentic AI solutions for EDA automation
Experience with CI/CD integration for physical design flows
Familiarity with compute farm management and job scheduling optimization
Knowledge of advanced packaging or multi-die integration flows
The base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
AI Your Way. Purpose-built Rack-Scale Connectivity.
Industry
Semiconductor Manufacturing
Company size
501-1,000 employees
Founded
2017
Headquarters
San Jose, CA
LinkedIn followers
56,125
Total funding
$206M
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Offices: San Jose, CA, US · Toronto, CA · Taipei, TW · Shanghai, CN · Haifa, IL
Connectivity solutionsSignal ConditioningPCIeHeterogeneous ComputeHyper-scale Data CenterNVMeEthernetCXLAIML
How much do Science & Research jobs in San Jose, CA pay?
Based on 678 listings with disclosed salaries, most science & research jobs in San Jose, CA pay between $100k–$260k per year. Individual offers vary with seniority, company size, and specialization.
How many Science & Research jobs are open in San Jose, CA right now?
There are currently 820 open science & research positions in San Jose, CA listed on Clera. New openings are added daily as companies post roles.
Which companies are hiring for Science & Research roles in San Jose, CA?
Companies currently hiring include Muon Space, Capital One, Hark Labs, Archer, Research and Innovation at San Jose State University, among others. Browse the listings above to see every active employer.
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