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Analog Devices is seeking a Digital Mixed Signal (DMS) Design Verification Engineer who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units. 

About the Role 

Key member of design verification team, which has both DMS and digital DV engineers. The candidate will be responsible for completing modeling & verification of large integrated products. The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible. 

Requirements 

• B.Tech/M.Tech with 2+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification using these behavioral models & digital RTL/PA/Gates. 

• Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal/RF building blocks such as Power Management, ADCs, DACs, PLL, bandgap references, oscillators, SerDes and related digital control and signal processing. 

• Hands on experience in developing verification plan, verification environments and verification/debug of complex mixed signal products at block & chip-top levels. 

• Exceptional interpersonal and communication skills, collaborate with multiple teams spread across the globe to get the work done. 

Responsibilities 

• Come up with verification strategy for a product after going through product requirements and design specifications. 

• Create models for analog/mixed-signal blocks for chip-top verification, tradeoff accuracy vs. speed. Validate models against actual design (self-checking tests). 

• Create verification plans, build verification environment, develop self-checking testcases. Bring up chip top mixed-signal verification environments (DMS DV). 

• Deploy industry standard SV/UVM based metric driven verification approach. 

• Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV, DFT etc.) for first pass silicon. 

• Support test and characterization teams in post-silicon validation. 

• Collaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM. 

Skill Set [Experience of following is desired, not all but most of them] 

• Modelling of analog blocks 

• SV-RNM 

• Familiarity with Analog/Mixed-Signal/RF design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision. 

• Experience and debug with digital simulators such as Cadence Xcelium/Synopsys VCS. 

• Experience with SV/UVM (agent creation, env building, score-boarding, RAL etc.). 

• Tracking of verification metrics(Vplan & Coverage) and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager. 

• Experience with languages/tools/software relating to product development is an added advantage. 

• C 

• Automation with scripting languages: Python/Perl/Shell etc.