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Static Timing Analysis (STA) Engineer

Company:

The Boeing Company

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Static Timing Analysis (STA) Engineer to join us as part of our Boeing Electronic Products team located in Tukwila, WA and at the heart of Boeing’s products - ASICs and FPGAs.

Our Electronics Products team goal is to be Boeing’s sole source for electronics. We’ve grown by over 400% and continue to have new opportunities to support more Boeing Platforms. We are seeking an experienced Static Timing Analysis Engineer that is ambitious and will thrive in a technology development environment and can work the full spectrum from research through flight insertion. We’re highly supportive of innovative thinking, we respect and acknowledge hard work, we recognize maturity and integrity, and we reward bottom-line achievement. At Boeing, we value your curiosity, your determination, and your imagination. #TheFutureIsBuiltHere

The work we do enables the missions and needs of our customers as we help Connect, Protect, Explore, and Inspire the world. Our team of engineers leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world. We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. Plus, we're applying the latest digital IC design processes with industry-best tools to enable applications that cut across every domain at Boeing.

Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line – approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems).

As a Static Timing Analysis (STA) Engineer you will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on the most critical programs across the Boeing Defense and Security enterprise. You will collaborate with other electronics groups across the company and around the world from the early design stages until signoff to help achieve first pass success. You will be working with a large physical design team within the company and outside of the company for timing convergence. Boeing STA engineers are required work with IP team, EDA vendors, and Foundry for the design closure.

Position Responsibilities

• Responsible for STA analysis and convergence throughout the ASIC cycle

• Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)

• Facilitate STA methodology in collaboration with other STA leaders

• Generate timing constraints for multiple ASICs and FPGAs

• Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis

• Responsible for intricate cross domain timing path closure

• Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints

• Programming skills with Python, TCL, Perl, Unix shell etc.

• Help train new engineers

This position is expected to be 100% onsite. The selected candidate will be required to work onsite in El Segundo, CA.

Our worksite participates in Boeing’s optional 9/80 schedule rotation. 9/80 is a rotation in which employees can work 9-hour shifts, 8 days per pay period (bi-weekly) and receive every other Friday off.

Travel may be required up to 10% of the time; Domestically and/or internationally depending on business needs.

Basic Qualifications (Required Skills/Experience)

• This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.

• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement

• 5+ years of experience with timing closure on ASICs and FPGAs

• Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow

• Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis

• Ability to work with large physical design team to make the timing convergence successful

Preferred Qualifications (Desired Skills/Experience)::

• Lead, Level 5: 15+ years of related work experience or an equivalent combination of education and experience

• 10 or more years of experience with timing closure on ASICs and FPGAs

• Completed multiple first-pass success ASIC tape-outs with intricacies (Cross clock domain, async crossing etc.)

• Experience in using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime)

• Fair knowledge of Synopsys Fusion Compiler, Formality (Cadence LEC), and other relevant tools (e.g. TCM, Fishtail)

• Synopsys physical design AI tool experience is a plus

• Experience leading static timing closure and training new hires

• Familiarity with space-based design techniques and radiation mitigation

• Understanding of design for testability (DFT) and its implications on timing

• Capable of working independently, self starter

• Proficiency with multiple scripting languages (Python, C SHELL, TCL)

• Capable of handling timing closure on multiple designs simultaneously

Typical Education/Experience

Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Senior, Level 5: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Relocation

This position offers relocation based on candidate eligibility.

Drug Free Workplace

Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.

Shift Work

This position is for 1st shift.

Union Representation

This is a union-represented position

Total Rewards

At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.

Pay is based upon candidate experience and qualifications, as well as market and business considerations.

Summary pay range for Lead (Level 4): $146,200 – $197,800

Summary pay range for Senior (Level 5): $176,800 - $239,200

Language Requirements:

Not Applicable

Education:

Bachelor's Degree or Equivalent

Relocation:

This position offers relocation based on candidate eligibility.

Export Control Requirement:

This position must meet U.S. export control compliance requirements. To meet U.S. export control compliance requirements, a “U.S. Person” as defined by 22 C.F.R. §120.62 is required. “U.S. Person” includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee.

Safety Sensitive:

This is not a Safety Sensitive Position.

Security Clearance:

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret Clearance Post-Start is required.

Visa Sponsorship:

Employer will not sponsor applicants for employment visa status.

Contingent Upon Award Program

This position is not contingent upon program award

Shift:

Shift 1 (United States of America)

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