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Bengaluru, Karnataka, India · On-site
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Perform SRAM memory layout development and physical verification for complex designs based on provided specifications. Optimize layout area and routing while addressing yield, reliability, and layout effects on circuit performance.
Requires 4 to 8 years of experience in SRAM layout using advanced CMOS processes. Candidates must hold a B.Tech, B.E, M.Tech, or M.E degree.
Role and Responsibilities
· Must have 4 - 8 years of experience in SRAM Layout in advanced CMOS process
· Should be able to perform SRAM Memory layout development and physical verification activities for complex designs as per provided specifications.
· Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
· Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
· Should have adequate knowledge of schematics, interface with circuit designer and CAD team.
· Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
Skills and Qualifications
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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