San Jose, California, United States · On-site
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Skills: Physical Verification, DRC, LVS, ERC, PERC
Chandler, Arizona, United States · On-site
$110k–$176k/yr
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Skills: Analog IC Design, Mixed-Signal Design, Cadence Virtuoso, SPICE Simulation, Spectre
Plano, Texas, United States · On-site
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Skills: IBM Assembler Language (HLASM), z/OS Operating System, Metal C, PL/X, JCL
San Jose, California, United States · On-site
$122k–$195k/yr
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Skills: SystemVerilog, RTL Design, PPA Optimization, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
San Jose, California, United States · On-site
$122k–$195k/yr
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Skills: Synthesis, DFT, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), SpyGlass CDC/RDC
San Jose, California, United States · On-site
$144k–$230k/yr
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Skills: Flip-chip-BGA Package Design, Project Management, Signal Integrity, Power Integrity, ASIC Design
San Jose, California, United States · On-site
$122k–$195k/yr
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Skills: System Verilog, UVM, Python, C/C++, RTL Verification
San Jose, California, United States · On-site
$144k–$230k/yr
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Skills: Signal Integrity, Power Integrity, SPICE, Electromagnetic Extraction, PDN Analysis
Bengaluru, Karnataka, India · On-site
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Skills: SOC Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, Static Timing Analysis
Shanghai, Shanghai, China · On-site
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Skills: DFT Architecture, Scan, Boundary Scan, Mem BIST, Logic BIST
Bengaluru, Karnataka, India · On-site
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Skills: SOC Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, Static Timing Analysis
Bengaluru, Karnataka, India · On-site
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Skills: SOC Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, Static Timing Analysis
Bengaluru, Karnataka, India · On-site
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Skills: Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, STA Closure
Bengaluru, Karnataka, India · On-site
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Skills: Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, STA Closure
Bengaluru, Karnataka, India · On-site
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Skills: Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, STA Closure
Bengaluru, Karnataka, India · On-site
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Skills: SOC Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, Static Timing Analysis
Bengaluru, Karnataka, India · On-site
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Skills: IC Design, ASIC Development, Logic Design, System Simulation, Synthesis
Bengaluru, Karnataka, India · On-site
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Skills: SOC Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, Static Timing Analysis
Bengaluru, Karnataka, India · On-site
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Skills: Physical Design, Floor-planning, Clock Tree Synthesis, Physical Verification, STA Closure
Bengaluru, Karnataka, India · On-site
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Skills: IC Design, ASIC Development, Logic Design, System Simulation, Synthesis
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Execute chip-level physical verification and resolve issues related to chip integration and assembly for advanced nodes. Develop verification methodologies and best practice guidelines for DRC, LVS, ERC, and PERC flows.
Requires a Bachelor's or Master's degree in Electrical Engineering with 6-8+ years of experience in physical design and verification. Must have hands-on experience with EDA tools like Calibre or ICV and proficiency in scripting languages.
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Broadcom is searching for a Physical Verification PD Engineer to join the Asic Products Division. This position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. More specifically, this position will require in-depth knowledge of Foundary rules, DFM and experience in silicon tape-out and respins.
Responsibilities:
Execution of Chip level Physical Verification & Issue Resolution
Work on setting up runsets for advance nodes and tool flows
Manage and guide rules related to top level floorplan, I/O and bump planning
Resolve physical design issues related to chip integration and assembly
Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
Develop best practice guidelines for physical verification flows and runtime optimizations
Preferred qualifications:
Bachelors's degree in Electrical Engineering and 8+ years of experience in physical design and verification
Master's degree in Electrical Engineering and 6+ years of experience in physical design and verification
Hands-on experience in running physical verification (LVS,DRC,ERC,PERC)
Experience in parasitic extraction tools i.e. StarRC, Quantus
Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools
Rule deck coding experience in ICV, Calibre or Pegasus EDA tools
Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience
Electrical Rule Checking (ERC/PERC): Analyze ESD (Electrostatic Discharge), latch-up, floating gates, and power-domain isolation vulnerabilities
Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet local and global density rules
Yield Enhancement (DFM): Implement Design for Manufacturability fixes, including critical area analysis (CAA), via-doubling, and edge-displacement rules.
Collaborate with physical design team to resolve critical top-level integration violations
Experience in scripting languages like Python, Tcl, or Perl
Excellent verbal and written communication skills
Must work in person at our San Jose site and no remote work allowed
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Broadcom provides semiconductors and infrastructure software for global organizations’ complex, mission-critical needs. We combine long-term R&D investment with superb execution to deliver the best technology, at scale. Through focus and expertise, Broadcom sets the standard in industries where technology breakthroughs shape markets. Our semiconductor and semiconductor-based solutions serve markets across networking connectivity, wireless device connectivity, servers and storage systems, broadband, and industrial. Broadcom’s infrastructure software solutions serve markets including private cloud, mainframe software, cybersecurity, enterprise software, and Fibre Channel storage area network management. With these core technologies, we help customers accelerate their innovation.
Offices: 3401 Hillview Ave, Palo Alto, California 94304, US
Broadcom provides semiconductors and infrastructure software for global organizations’ complex, mission-critical needs. We combine long-term R&D investment with superb execution to deliver the best technology, at scale. Through focus and expertise, Broadcom sets the standard in industries where technology breakthroughs shape markets. Our semiconductor and semiconductor-based solutions serve markets across networking connectivity, wireless device connectivity, servers and storage systems, broadband, and industrial. Broadcom’s infrastructure software solutions serve markets including private cloud, mainframe software, cybersecurity, enterprise software, and Fibre Channel storage area network management. With these core technologies, we help customers accelerate their innovation.
Offices: 3401 Hillview Ave, Palo Alto, California 94304, US
