Senior DFT Engineer

Role Overview

We are looking for a Senior DFT Engineer with solid hands-on experience to own key aspects of DFT implementation and verification for advanced SoC designs. You will drive DFT features to achieve high test coverage while optimizing for test time and power.

What You’ll Do

• Develop and implement DFT architecture including scan insertion, compression, and hierarchical DFT.
• Generate and optimize ATPG patterns for various fault models (stuck-at, transition, path delay, etc.) and perform failure diagnosis.
• Design, integrate, and verify MBIST controllers, repair mechanisms (BISR), and memory test strategies.
• Implement and verify Boundary Scan (BSCAN), JTAG, and IJTAG (IEEE 1687) infrastructure.
• Perform DFT static timing analysis (STA), constraint development, and timing closure in collaboration with PD teams.
• Execute DFT verification including pre-silicon simulations and Gate-Level Simulation (GLS).
• Support silicon bring-up, ATE (Automated Test Equipment) pattern validation, and post-silicon debug.
• Work closely with cross-functional teams (RTL, Verification, Physical Design, Test Engineering) to resolve DFT issues.
• Analyze coverage metrics and improve test quality.

What We’re Looking For

• Bachelor’s/Master’s degree in Electronics/Electrical Engineering.
• 4-7 years of experience in DFT for SoC/ASIC designs.
• Strong proficiency in ATPG, MBIST, LBIST, scan compression,BSCAN and IJTAG.
• Experience with industry tools for DFT insertion, pattern generation, and simulation.
• Hands-on silicon bring-up and debug experience.
• Proficiency in scripting (Python,Tcl, Perl) for automation.