DFT Engineer

Role Overview

We are seeking a motivated and driven DFT Engineers to join our semiconductor design team. In this role, you will take direct ownership of implementing and verifying Design-for-Test (DFT) features across complex SoCs and ASICs. You will drive tasks independently to ensure high test coverage, manufacturability, and first-pass silicon quality.This is a great opportunity to build world-class chiplets and work on cutting-edge silicon architectures.

What You’ll Do

• Execute scan insertion, scan chain stitching, and DFT rule checking (DRC) using industry-standard tools.
• Generate and simulate ATPG (Automatic Test Pattern Generation) patterns targeting stuck-at and transition fault models.
• Implement and verify MBIST (Memory Built-In Self-Test) structures for embedded memories.
• Deploy and validate JTAG and Boundary Scan (BSCAN/IEEE 1149.1) architectures at the chip level.
• Run gate-level DFT simulations and perform detailed coverage analysis to close test gaps.
• Debug silicon bring-up failures by analyzing test data logs and isolating physical defects.
• Interface directly with RTL, verification, and physical design teams to resolve timing, power, and area trade-offs for DFT.
• Own the documentation of DFT architecture implementation details and post-silicon test procedures.

What We’re Looking For

• Bachelor’s/Master’s degree in Electronics/Electrical Engineering, VLSI, or a related field.
• 1–3 years of hands-on, practical experience in DFT implementation and verification.
• Solid understanding of digital design fundamentals, Verilog/SystemVerilog, and standard SoC design flows.
• Demonstrated experience with basic ATPG, MBIST, scan compression, and fault modeling.
• Direct exposure running Synopsys (TestMAX), Siemens (Tessent), or Cadence DFT EDA tools.
• Strong analytical, debugging, and cross-functional communication skills.

Good to Have

• Practical knowledge of IJTAG (IEEE 1687) architectures.
• Proficiency in writing scripts using Tcl, Python, or Perl to automate DFT tool flows.