Principal/Senior Manager ASIC Verification

The Senior Manager of digital design and digital verification leads a team responsible for designing/verifying complex mixed-signal ICs that integrate Analog & digital components. This role demands deep technical expertise, strategic leadership, and cross-functional collaboration to ensure first-pass silicon success

Your role
Key responsibilities in your new role

• Architecture and design of digital blocks for integration CMOS IC’s
• Specification and design of digital blocks at RTL level and addition of DfT concept onto the design
• Synthesis, block verification and gate level analysis of implemented digital blocks for on-silicon integration
• Implementation and verification of ECO’s on existing designs
• Technically lead digital design tasks in strong cooperation with project technical lead and project manager
• Develop testbenches using System Verilog and UVM for functional and power aware RTL
• Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage.
• Develop test plan, UVM based test sequences, layered sequences, virtual sequencers
• Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation.
• Manage and mentor a team of digital and digital DV engineers.
• Drive hiring, performance reviews, and career development.
• Foster a culture of technical excellence and innovation.

Your profile
Qualifications and skills to help you succeed 

• Master’s or PhD in Electrical Engineering or related field.
• 10+ years of experience in mixed-signal IC verification, with 3–5 years in a leadership role.
• Knowledge of relevant digital design flow tools for synthesis, LEC (logic equivalence check), CDC/RDC (clock/reset domain crossing), linting, synthesis constraining
• Proficiency in Verilog, Verilog-A/AMS, UVM, and scripting languages (Python, Perl, Tcl).

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