ASIC Engineer, EDA Infrastructure
- Location
- Sunnyvale, CA
- Workplace
- On-site
- Compensation
- $114k – $172k
About this role
Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. We are looking for individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build System on Chip (SoC) and IP for data center applications.
$114,000/year to $172,000/year + bonus + equity + benefits
Responsibilities
- Front End implementation flow development and support
- Physical Design implementation flow development and support
- RTL2GDS flow development and support
- Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation
- Work with EDA vendors on new tools/technology and new features evaluation and adoption
- Manage the internal EDA license requests, installation and license forecast as well as EDA tool installation and maintenance
- Work with internal infrastructure team on compute grid, storage management and job scheduling architecture, efficiency and maintenance
- Work with internal infrastructure team on adapting internal infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management and reporting
Minimum Qualifications
- Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
- Bachelor's degree in Computer Science, Electrical Engineering, or Computer Engineering, in a relevant technical field, or equivalent practical experience
- 2+ years of experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments
- Experience with ASIC EDA infrastructure (compute, storage, job scheduling) management, maintenance and support
- Experience with developing and supporting solutions for ASIC design environment and infrastructure
- Experience with communicating across functional internal teams and with vendors
Preferred Qualifications
- Experience designing tools and workflows with a focus on usability and end-user productivity
- Knowledge of front-end and back-end ASIC tools and flows
- Experience setting up EDA infrastructure from scratch
- Experience with RTL design using SystemVerilog or other HDL
$114,000/year to $172,000/year + bonus + equity + benefits
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