STA - Static Timing Analysis Lead (8+ Years)

Position Overview

We are seeking an experienced STA Lead with strong expertise in Static Timing Analysis for complex ASIC/SoC designs. The ideal candidate will be responsible for driving timing closure activities across block and full-chip level designs while collaborating closely with RTL, Physical Design, DFT, CTS, and Signoff teams.

This role requires deep understanding of timing methodologies, advanced process nodes, low-power design considerations, and full-chip timing signoff flows for high-performance semiconductor products.

• Lead STA activities for block-level and full-chip ASIC/SoC designs.
  
• Drive timing closure across synthesis, place-and-route, CTS, and signoff stages.
  
• Perform:
  
• Static Timing Analysis
  
• Timing constraint development
  
• Timing debugging
  
• Timing signoff
  

• Analyze and resolve setup, hold, noise, and clock-related timing violations.
  
• Work closely with RTL, Physical Design, DFT, and Architecture teams to achieve timing closure targets.
  
• Validate timing constraints and ensure accurate SDC implementation.
  
• Perform timing analysis across multiple modes and corners (MMMC).
  
• Support ECO implementation and timing optimization activities.
  
• Participate in design reviews and signoff meetings.
  
• Mentor junior engineers and drive best practices for STA methodologies.
  

Requirements

Required Skills & Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
  
• 8+ years of hands-on experience in STA and timing closure for ASIC/SoC designs.
  
• Strong expertise in:
  
• Static Timing Analysis
  
• Timing Closure
  
• MMMC Analysis
  
• SDC Constraints
  
• ECO Flows
  
• Clock Tree Analysis
  
• Good understanding of:
  
• RTL-to-GDSII flow
  
• Physical Design
  
• CTS
  
• Signal Integrity
  
• Low-power timing analysis
  
• Experience with advanced semiconductor technology nodes.
  
• Strong debugging and analytical capabilities.
  
• Ability to lead timing signoff activities independently.
  

Preferred Skills

• Experience with CPU/GPU/AI/Networking/High-Performance Compute SoCs.
  
• Exposure to low-power and multi-voltage designs.
  
• Familiarity with DFT timing closure interactions.
  
• Experience handling full-chip timing signoff.
  
• Knowledge of scripting languages such as TCL, Perl, or Python.
  

Tools & Technologies

• PrimeTime
  
• Tempus
  
• ICC2 / Innovus
  
• StarRC / Quantus
  
• Verilog/SystemVerilog
  
• TCL / Perl / Python
  
• SpyGlass / Timing Signoff Tools
  

Key Competencies

• Strong timing closure expertise
  
• Problem-solving and debugging capabilities
  
• Leadership and mentoring skills
  
• Cross-functional collaboration
  
• Ownership mindset
  
• Strong attention to detail and quality