SoC Analog Integration Architect

Our Automotive Microcontroller R&D team is looking for an experienced SoC Analog Integration Architect to join the Chip-Level Architecture team and own the analog IP co-integration strategy for our next-generation automotive microcontroller platform

Your role
Key responsibilities in your new role

·         Own the chip-level integration strategy for all analog IPs on the platform — ensuring each IP fits correctly within the clock, reset, and power domain framework.

·         Drive the floorplan strategy for analog IP placement and define the reference distribution architecture across the chip, with particular focus on ADC and SMIF interface integrity.

·         Perform early model-based and transistor-level simulation for power and signal integrity verification, de-risking analog integration before silicon.

·         Define noise budget allocation across analog IPs and establish co-existence rules for analog-digital IP proximity on the same die.

·         Review analog IP scalability decisions across all product variants to ensure the platform can be reused efficiently.

·         Serve as the technical lead for all analog IP design reviews and chip integration sign-off throughout the IP development phase.

·         Work with PHY and PMIC vendors to verify electrical compatibility with the platform through model-based verification.

·         Maintain technical architecture documentation in compliance with ISO 26262 requirements.

Your profile
Qualifications and skills to help you succeed 

·         Bachelor's or Master's degree in Electrical Engineering or related field.

·         At least 10 years of industry experience in semiconductor development with a strong focus on analog circuit design and mixed-signal subsystem integration.

·         Good knowledge of analog IP development — ADCs, data converters, SMIF interfaces, LDOs, bandgap references — and their chip-level integration requirements.

·         Experience with model-based and transistor-level simulation for power and signal integrity analysis.

·         Understanding of floorplan constraints for analog IP placement, guard ring requirements, substrate coupling, and noise injection budgets.

·         Familiarity with PHY and PMIC compatibility assessment at chip and system level.

·         Familiarity with ISO 26262 documentation standards.

·         Pro-active collaborative attitude with strong communication skills in a global multi-cultural team.

·        Fluent English required; German is a plus.

You are best equipped for this task if you have:

·         Defined analog IP integration strategies including reference distribution architecture and floorplan placement recommendations for ADC-heavy platforms.

·         Hands-on simulation experience for AMS co-existence analysis — noise injection budgets, aggressor-victim assessment, substrate coupling.

·         Reviewed analog IP scalability decisions (e.g. ADC channel count, SMIF interface count) across a platform product family.

·         Participated in analog IP design reviews and chip integration reviews across the full IP development lifecycle.

·         Worked with PHY and PMIC vendors on model-based electrical compatibility verification.

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