Senior Hardware Design Engineer
About this role
Senior Hardware Design Engineer
Department: US Jobs
Employment Type: Permanent
Location: West Coast, United States
Description
Key Responsibilities
As a Senior Hardware Design Engineer, you will: -
- Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations
- Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
- Deploy your designs onto the latest FPGA development platforms for validation and system integration
- Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
- Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA
Skills, Knowledge and Expertise
Essential:
- Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
- A strong skillset in delivering digital designs in the ASIC and FPGA industry
- Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
- Track record in collaborating across teams to produce integrated solutions
- Experience in technical documentation writing – design specifications, user guides, verification plans
- Expert user of EDA tools for simulation and synthesis
- Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
- Familiarity with the AMBA bus protocols
- Understanding of UVM verification techniques or practical experience using UVM for IP verification
- Experience using C++/SystemC for design modelling and integration
- Experience with high speed interfaces such as PCI-E or JESD
- Knowledge of a scripting language, such as Python
- Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
- Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools
Company at a glance
AccelerComm is a leading provider of high-performance, error-resilient physical layer solutions for 5G Non Terrestrial Networks (NTN). Experts in specialist Radio Access Networks (RAN) applications, AccelerComm delivers solutions with cutting-edge performance and power efficiency, utilising next generation compute platforms.
The company’s comprehensive portfolio ranges from customisable signal processing components through to complete physical layer solutions, implemented over a wide range of platforms, including software, AI Engines, FPGA, and ASIC-ready IP cores. Its modular approach allows seamless integration based on O-RAN, SCF and 3GPP standards.
AccelerComm’s solutions can be configured for a wide range of applications, optimizing aspects such as power consumption, latency, reliability, and resilience. Its technology addresses the unique challenges of NTN satellite communications, offering space-hardened, field-proven implementations that meet stringent SWaP (Size, Weight and Power) requirements.
Through continuous innovation, AccelerComm ensures its customers have access to the latest advancements in physical layer technology, supporting the development of tomorrow’s high-performance, low-power networks.
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