Chiplet Physical Design Engineer

<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>We are seeking a Physical Design Engineer with strong experience in synthesis and place-and-route (PnR) for high-speed CPU and SoC designs. You will collaborate with world-class engineers across Tenstorrent’s global teams in the USA, Japan, and beyond—contributing to some of the industry’s most technically ambitious design projects.</p> <p>&nbsp;</p> <p>This is open to hybrid in Tokyo, Japan</p> <p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p><strong>Who You Are&nbsp;</strong></p> <ul> <li>A technically strong engineer with a passion for design excellence and precision.</li> <li>A collaborative problem-solver who thrives in cross-functional global environments.</li> <li>A self-starter who can balance detail orientation with big-picture project goals.</li> <li>A structured thinker skilled at planning, tracking, and executing design schedules.</li> <li>A lifelong learner eager to adopt new technologies and methodologies.</li> </ul> <p><strong>What We Need</strong></p> <ul> <li>Advanced degree in Electrical, Computer Engineering, or Computer Science.</li> <li>Proven experience with IC design tools (Synopsys or Cadence) for synthesis, PnR, STA, and closure.</li> <li>Strong understanding of timing and power convergence methodologies.</li> <li>Hands-on experience with chip-level physical design verification and signoff checks.</li> <li>Proficiency in TCL scripting and at least one additional programming language (e.g., Python).</li> </ul> <p><strong>What You Will Learn</strong></p> <ul> <li>How to build scalable multi-chiplet physical design flows for advanced SiP architectures.</li> <li>Expertise in 5nm and below technologies and high-frequency CPU implementation.</li> <li>Strategies for achieving efficient PPA convergence across complex SoC designs.</li> <li>How to integrate design work into global, cross-functional hardware programs.</li> <li>Best practices for automating and improving physical design productivity.</li> </ul> <p>&nbsp;</p> <p><em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></p><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. &nbsp;Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). &nbsp; These requirements apply to persons located in the U.S. and all countries outside the U.S. &nbsp;As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. &nbsp;If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.</em></p></div>