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ASIC/SOC DFT Engineer (Silicon Engineering)
full-timeBastrop

Summary

Location

Bastrop

Type

full-time

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About this role

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.


ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)



At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 




We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   



RESPONSIBILITIES:



  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools

  • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems

  • Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage

  • Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals

  • Run and debug non-timing and SDF annotated gate level simulations

  • Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation

  • Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon


BASIC QUALIFICATIONS:



  • Bachelor’s degree in electrical engineering, computer engineering or computer science

  • 1+ years of professional experience working with ASICs

  • Experience in scan insertion or DFT setup


PREFERRED SKILLS AND EXPERIENCE:



  • Understanding of ASIC design flow, methodologies, physical design, and verification

  • Experience with high reliability design and implementations

  • Good scripting skills (csh/bash, Perl, Python etc.)

  • Familiar with implementation or integration of design blocks using Verilog/SystemVerilog

  • Familiar with UPF (unified power format), formal verification, and DRC rule checking experience

  • Ability to work in a dynamic environment with changing needs and requirements

  • Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis

  • Enjoys being challenged and learning new skills



ADDITIONAL REQUIREMENTS:



  • Must be willing to work extended hours and weekends as needed

ITAR REQUIREMENTS:



  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  


SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.


Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [email protected]

Other facts

Tech stack
ASIC Design,DFT Setup,Scan Insertion,Synthesis Tools,ATPG Analysis,Gate Level Simulation,Verilog,SystemVerilog,Scripting,Physical Design,Verification,High Reliability Design,Dynamic Environment,Team Player,Learning New Skills

About SpaceX

SpaceX designs, manufactures and launches the world’s most advanced rockets and spacecraft. The company was founded in 2002 by Elon Musk to revolutionize space transportation, with the ultimate goal of making life multiplanetary.

SpaceX has gained worldwide attention for a series of historic milestones. It is the only private company ever to return a spacecraft from low-Earth orbit, which it first accomplished in December 2010. The company made history again in May 2012 when its Dragon spacecraft attached to the International Space Station, exchanged cargo payloads, and returned safely to Earth — a technically challenging feat previously accomplished only by governments. Since then Dragon has delivered cargo to and from the space station multiple times, providing regular cargo resupply missions for NASA.

For more information, visit www.spacex.com.

Team size: 1,001-5,000 employees
LinkedIn: Visit
Industry: Aviation and Aerospace Component Manufacturing
Founding Year: 2002

What you'll do

  • The engineer will evaluate design readiness for scan insertion and integrate DFT fabrics within subsystems. They will also run ATPG analysis and collaborate with various teams to ensure high-quality scan coverage in silicon.

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Frequently Asked Questions

What does a ASIC/SOC DFT Engineer (Silicon Engineering) do at SpaceX?

As a ASIC/SOC DFT Engineer (Silicon Engineering) at SpaceX, you will: the engineer will evaluate design readiness for scan insertion and integrate DFT fabrics within subsystems. They will also run ATPG analysis and collaborate with various teams to ensure high-quality scan coverage in silicon..

Why join SpaceX as a ASIC/SOC DFT Engineer (Silicon Engineering)?

SpaceX is a leading Aviation and Aerospace Component Manufacturing company.

Is the ASIC/SOC DFT Engineer (Silicon Engineering) position at SpaceX remote?

The ASIC/SOC DFT Engineer (Silicon Engineering) position at SpaceX is based in Bastrop, Texas, United States. Contact the company through Clera for specific work arrangement details.

How do I apply for the ASIC/SOC DFT Engineer (Silicon Engineering) position at SpaceX?

You can apply for the ASIC/SOC DFT Engineer (Silicon Engineering) position at SpaceX directly through Clera. Click the "Apply Now" button above to start your application. Clera's AI-powered platform will help match your profile with this opportunity and guide you through the application process. You can also learn more about SpaceX on their website.