About this role
Architecture & Micro-Architecture
· Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.
· Collaborate with various software teams to co-optimize hardware features for AI workloads.
· Collaborate with RTL designers to identify complex technical issues/risks. Review and guide RTL implementation, ensuring consistency with architectural intent and timing/power goals
· Collaborate with Physical-design teams for Area/Floorplan refinement, Timing targets etc.
· Define and document interface specifications, control/status logic, and pipeline structures.
· Lead PPA analysis and trade-off discussions across RTL and architecture.
AI Workloads & HW-SW Co-Design
· Collaborate closely with various software to co-optimize hardware features for real-world AI inference workloads.
· Incorporate considerations such as, quantization, sparsity, dataflow, scheduling, memory bandwidth into architectural decisions.
· Guide hardware features that improve programmability, debuggability, and long-term software scalability.
Modelling & Analysis
· Develop and maintain high-level architecture and performance models.
· Use simulation and architectural models to guide RTL-level improvements.
· Validate model predictions against RTL or emulation results and refine accordingly.
· Strong understanding of AI inference workloads, dataflows, quantization, and memory/bandwidth bottlenecks in edge deployments
#LI-2734Other facts
About NXP Semiconductors
We anticipate tomorrow’s needs—navigating a changing world by bringing together technology's brightest minds to build game-changing solutions that propel us forward.
NXP Semiconductors N.V. (NASDAQ: NXPI) is the trusted partner for innovative solutions in the automotive, industrial & IoT, mobile, and communications infrastructure markets. NXP's "Brighter Together" approach combines leading-edge technology with pioneering people to develop system solutions that make the connected world better, safer, and more secure. The company has operations in more than 30 countries and posted revenue of $12.61 billion in 2024. Find out more at www.nxp.com.
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What you'll do
- The engineer will define the product architecture for compute, memory, interconnect, and high-speed interface subsystems within an AI inference chip, collaborating with software teams for workload co-optimization. Responsibilities also include guiding RTL implementation, reviewing technical risks, defining interface specifications, and leading Power, Performance, and Area (PPA) analysis.
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