Job Details:

Job Description: 

This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.

The Test & Manufacturing Engineer is responsible for driving and optimizing the testability and manufacturability of integrated circuits from early feasibility through high‑volume production ramp. This role plays a critical part in validating silicon, enabling production readiness, and ensuring robust manufacturing performance across fab, assembly, and test operations.

Key Responsibilities

Testability & Design Integration

• Lead the development of testability and manufacturability strategies throughout the product lifecycle—from feasibility to production ramp.
• Contribute to the design, development, and validation of testability circuits, test flows, and methodologies for new silicon products.
• Collaborate closely with design, DFx, and product development teams to root‑cause functionality, performance, and test issues.

Silicon Evaluation & Debug

• Evaluate new designs using Automatic Test Equipment (ATE) and debug complex test methods for product enablement.
• Perform ATE characterization, analyze device performance, and translate results into accurate datasheet specifications.
• Identify and resolve yield, margin, and performance issues by analyzing silicon behavior versus design requirements.

Test Hardware & Software Development

• Develop and debug complex software programs used to convert design validation vectors and control ATE systems.
• Create, validate, and optimize production test hardware solutions, including load boards, probe cards, and test fixtures.

Manufacturing Readiness & Yield Optimization

• Drive high‑volume manufacturing (HVM) readiness, partnering with fab, assembly, and test factories to support engineering samples, wafer starts, qualification plans, and test-site certification.
• Guarantee manufacturability across process and product variations by analyzing process and specification corners.
• Lead yield improvement activities, including fallout analysis, bin‑split optimization, die-level cherry pick (DLCP), and test content optimization.

Process, Quality, and Cost Optimization

• Ensure component performance meets specification by testing, validating, modifying, and redesigning circuits where required.
• Balance quality and cost by developing and applying strategies that optimize test methods, equipment capability, and overall production efficiency.
• Drive test time reduction through data‑driven analysis to improve cost, throughput, and product margin.

Cross‑Functional Collaboration

• Work closely with process development, fab engineering, assembly, reliability, and factory teams to support silicon bring-up and resolve production blockers.
• Lead or participate in engineering task forces addressing product issues, manufacturing challenges, and test‑coverage gaps.
• Analyze early customer returns to identify test escape mechanisms and close test holes.

Additional Responsibilities

• Support new product introduction (NPI) activities, including fab process targeting and product/process optimizations.
• Conduct capacity analysis and support wafer start planning for production ramp.
• Optimize supply chain outcomes by analyzing post‑silicon data, including binning behavior and downstream yield.

Qualifications:

Minimum qualifications are required to be initially considered for this position.  Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
•  9 years of experience in:
  • PC architecture, microprocessor architecture, and DFX (Design for Test/Debug/Manufacturing) principles.
  • At least one higher‑level programming language such as Visual Basic, C/C++, Perl, or a similar programming language—gained through industry experience or graduate‑level projects.
• Advanced English level.

• Must have permanent-unrestricted right to work in Costa Rica

Preferred Qualifications:

• Experience with Automatic Test Equipment (ATE), test program development, or silicon validation workflows.
• Familiarity with Design for Test/Debug/Manufacturing (DFT/DFD/DFM) methodologies used in semiconductor product development.
• Experience in post‑silicon validation, hardware characterization, or yield analysis.
• Proficiency in scripting languages (Python, Perl, Bash) for test automation and data analysis.
• Experience developing or debugging test hardware (load boards, probe cards, fixtures).
• Knowledge of production test flows, binning strategies, and manufacturing quality processes.
• Background in analyzing silicon performance versus specification and defining datasheet limits.
• Drive process improvements, reduce test time, and optimize cost, quality, and throughput.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Costa Rica)

Primary Location: 

Costa Rica, San Jose

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.