About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
The Cadence Artisan Foundation IP group team develops industry leading Foundation IP that enable customers to tape-out their design with industry leading Power, Performance and Area. Artisan Foundation IP group develops embedded SRAMs, standard cells and general purpose IOs which can be used to build a variety of designs across different foundries with ease and meeting the best PPA. Arisan Foundation IP is used extensively in CPU compute, Automotive, Infra and High Performance Compute chips across the semiconductor industry.
We are growing our Foundation IP team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our products. At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged? Join the High-Performance Culture at Cadence.
As an individual working on the development flows, you will innovate on the efficiency of developing embedded SRAM and other memories
Responsibilities include:
• Flow innovation and improvements
• Development efficiency of embedded SRAM
• Work closely with memory engineers, software team and EDA teams to build world class development flows
• Work with teams to enable efficient ways of developing memory compilers
• Build prototypes for working efficiency
• Work closely with leading architects to enable architecture evaluation flows
• Leverage Agentic AI or existing AI-based EDA capabilities to reduce development effort
Qualifications:
• BS/MS in EE, CE or related majors
• Knowledge of embedded SRAM memory compilers
• Knowledge of characterization and EDA view generation flows
• Experience in developing efficient development flows
• Good grasp of programming languages and associated tools like python, java, make files, perl etc.
Additional recommended qualifications:
• Understanding of Foundry business and how the efficiency matters to the development
• Experience on memory validation and quality checks
• Strong knowledge of how the memories are used in customer designs
• Knowledge of EDA views in memory compilers
• Working knowledge of memory compiler development
The annual salary range for Vermont is $163,800 to $304,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Other facts
About Cadence Design Systems
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
What you'll do
- The role involves innovating on the efficiency of developing embedded SRAM and other memories, as well as improving development flows. Collaboration with memory engineers, software teams, and EDA teams is essential to build world-class development processes.
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