Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
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Job responsibilities:
Job Description: Layout Design
Work Location : Bangalore
Work experience : 4+ Years of experience or relevant experience
CV to [email protected]
Responsibilities:
• Custom layout design for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts.
• Perform physical verifications like DRC/LVS/Reliability and fixing violations
• Lead custom layout efforts for DDR IO development - Understand design requirements and work closely with the design team and successfully deliver Analog layouts.
• Would be required to lead/mentor a small team of engineers towards a successful IP delivery.
• Perform physical verifications like DRC/LVS/Reliability and fixing violations
Requirements
• Hands on layout experience in various analog IP like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
• Knowledge of various analog layout techniques like matching, shielding etc.,
• Good understanding of DSM technology methodology, issues etc.,
• Having worked on latest technology nodes, 28nm and below, is desired.
• Must have good communication skills and should be team player.
• Scripting and automation experience is a plus.
• Hands on layout experience in various analog IP like High-speed Analog (Serdes), Data converters, power management and PLL etc.
• Understanding layout effects on the circuit such as speed, capacitance, power, and area etc.,
• Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario.
• Good understanding of DSM technology methodology, issues etc.,
• Having worked on latest technology nodes, 28nm and below, is desired.
• Must have good communication skills and should be team player.
• Scripting and automation experience is a plus.
• Good communication skills, documentation, and presentation skills.
• Strong analytical and problem-solving skills.
Qualifications
Behavioral skills required.
Regards
K Madhu Prasad
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.
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