Timing Design Engineer
full-time•San Diego
About this role
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something.
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
BS degree in technical discipline with minimum 3 years of relevant experience.
Proven knowledge of the ASIC design timing closure flow and methodology. 2+ years of experience in writing ASIC timing constraints and timing closure. Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and management. Proficient in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite – you will be collaborating with many diverse groups at Apple. The ideal candidate will be a self-starter and highly motivated to be successful at Apple.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Minimum Qualifications
BS degree in technical discipline with minimum 3 years of relevant experience.
Preferred Qualifications
Proven knowledge of the ASIC design timing closure flow and methodology. 2+ years of experience in writing ASIC timing constraints and timing closure. Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and management. Proficient in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite – you will be collaborating with many diverse groups at Apple. The ideal candidate will be a self-starter and highly motivated to be successful at Apple.
Other facts
Tech stack
ASIC Design,Timing Closure,STA Tools,Timing Constraints,Scripting Languages,Signal Integrity,Physical Design,Collaboration,Communication Skills,Self-Starter,Timing Analysis,Synthesis,DFT,Backend Methodology,Process Variations,Timing Corners
About Apple
We’re a diverse collective of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. And the same innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it. This is where your work can make a difference in people’s lives. Including your own.
Apple is an equal opportunity employer that is committed to inclusion and diversity. Visit apple.com/careers to learn more.
Team size: 10,001+ employees
Website: http://www.apple.com/careers
LinkedIn: Visit
Industry: Computers and Electronics Manufacturing
Founding Year: 1976
What you'll do
- As an ASIC STA Engineer, you will be responsible for timing sign-off and the development of sign-off flow. You will interact with various teams to ensure timing closure and manage timing constraints.
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Frequently Asked Questions
What does a Timing Design Engineer do at Apple?
As a Timing Design Engineer at Apple, you will: as an ASIC STA Engineer, you will be responsible for timing sign-off and the development of sign-off flow. You will interact with various teams to ensure timing closure and manage timing constraints..
Why join Apple as a Timing Design Engineer?
Apple is a leading Computers and Electronics Manufacturing company.
Is the Timing Design Engineer position at Apple remote?
The Timing Design Engineer position at Apple is based in San Diego, California, United States. Contact the company through Clera for specific work arrangement details.
How do I apply for the Timing Design Engineer position at Apple?
You can apply for the Timing Design Engineer position at Apple directly through Clera. Click the "Apply Now" button above to start your application. Clera's AI-powered platform will help match your profile with this opportunity and guide you through the application process. You can also learn more about Apple on their website.