SoC Power Flow Methodology Engineer
full-time•Beaverton, Cupertino
About this role
Do you love creating solutions for complex challenges? As part of the Low Power group within Silicon Technologies, you’ll help deliver cutting-edge new technology and capabilities for low-power chip design that fuels Apple’s next-generation chips!
In this role, as a member of our dynamic group, you will be responsible for the development and enhancement of our low-power flows, providing designers new capabilities in terms of power domains unseen in previous chips, while working on highly visible products used by millions of people every day!
As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies. The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R. Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.
A minimum of a bachelor's degree in relevant field and a minimum of 10 years of relevant industry experience.
Good understanding of VLSI designs and SOC design flows. Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions. Strong background with flow development and/or object-oriented language algorithm design such as Python / C++ / Java. Solid understanding and proven track record using modern software testing and development practices. Good written/verbal communications skills are required. Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus.
Description
As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies. The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R. Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.
Minimum Qualifications
A minimum of a bachelor's degree in relevant field and a minimum of 10 years of relevant industry experience.
Preferred Qualifications
Good understanding of VLSI designs and SOC design flows. Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions. Strong background with flow development and/or object-oriented language algorithm design such as Python / C++ / Java. Solid understanding and proven track record using modern software testing and development practices. Good written/verbal communications skills are required. Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus.
Other facts
Tech stack
VLSI Designs,SoC Design Flows,Scripting,Low-Power Domain-Specific Knowledge,Software Solutions,Flow Development,Object-Oriented Language,Algorithm Design,Python,C++,Java,Software Testing,Development Practices,Tcl,Perl,EDA Tools,GUI Development
About Apple
We’re a diverse collective of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. And the same innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it. This is where your work can make a difference in people’s lives. Including your own.
Apple is an equal opportunity employer that is committed to inclusion and diversity. Visit apple.com/careers to learn more.
Team size: 10,001+ employees
Website: http://www.apple.com/careers
LinkedIn: Visit
Industry: Computers and Electronics Manufacturing
Founding Year: 1976
What you'll do
- As a Power Flow Methodology Engineer, you will develop and enhance low-power flows and provide designers with new capabilities. You will also be responsible for the architecture, implementation, and verification of new low-power design and verification flows.
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Frequently Asked Questions
What does a SoC Power Flow Methodology Engineer do at Apple?
As a SoC Power Flow Methodology Engineer at Apple, you will: as a Power Flow Methodology Engineer, you will develop and enhance low-power flows and provide designers with new capabilities. You will also be responsible for the architecture, implementation, and verification of new low-power design and verification flows..
Why join Apple as a SoC Power Flow Methodology Engineer?
Apple is a leading Computers and Electronics Manufacturing company.
Is the SoC Power Flow Methodology Engineer position at Apple remote?
The SoC Power Flow Methodology Engineer position at Apple is based in Beaverton, Oregon, United States and Cupertino, California, United States. Contact the company through Clera for specific work arrangement details.
How do I apply for the SoC Power Flow Methodology Engineer position at Apple?
You can apply for the SoC Power Flow Methodology Engineer position at Apple directly through Clera. Click the "Apply Now" button above to start your application. Clera's AI-powered platform will help match your profile with this opportunity and guide you through the application process. You can also learn more about Apple on their website.