Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture!

Description

Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC reports is key to finding the fastest way to complete the layout, exceeding engineering specifications and expectations.

Minimum Qualifications

BS and a minimum of 3 years relevant industry experience.

Preferred Qualifications

Experience in analog/mixed-signal layout design, with a focus on deep submicron CMOS circuits and FinFET technologies. Programming/scripting knowledge in SKILL, Perl, TCL, Shell, and/or Python. Familiar with Machine Learning and AI concepts. Proven Expertise in implementing analog layout designs, achieving tight matching, low noise, and low power consumption. Must recognize failure-prone circuit and layout structures, have experience with analog and DFM standards, and be able to identify the best approach to solving problems. High Proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly. Technical understanding of IR drop, RC delay, electromigration, self-heating, and coupling capacitance. High Proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.). Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager). Excellent communication skills and ability to work with cross-functional teams. Cadence Innovus. CAD Automation experience. PCell creation experience. MSEE or Ph.D. in Electrical and Computer Engineering.